Modular, portable data processing terminal for use in a radio frequency communication

ABSTRACT

Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network. The disclosed modular design also provides for automatic selection from a variety of available built-in and externally mounted antennas based on the particular type of radio transceiver(s) selected.

CROSS-REFERENCE TO RELATED APPLICATIONS Claiming Benefit Under 35 U.S.C.120

This application is a continuation-in-part application of the following:

-   -   1. U.S. application Ser. No. 07/898,908 (Attorney Docket Nos. 92        P 447 & DN36767XZAA), by Koenck et al., filed Jun. 12, 1992,        which is itself a continuation-in-part application of U.S.        application Ser. No. 07/835,718 (Attorney Docket Nos. 92 P 148 &        DN36767XZA), by Koenck et al., filed Feb. 12, 1992, now        abandoned.    -   2. U.S. application Ser. No. 08/071,555 (Attorney Docket Nos.        10168US04 & DN36767XZX), by Koenck et al., filed Jun. 4, 1993,        which is in turn a continuation application of U.S. application        Ser. No. 07/660,615 (Attorney Docket Nos, 91 P 398 & DN36767XZ),        by Danielson et al., filed Feb. 25, 1991, now U.S. Pat. No.        5,218,187, which is itself a continuation-in-part of:        -   a. U.S. application Ser. No. 07/467,096 (Attorney Docket            Nos. 91 P 402 & DN37139), by Koenck et al., filed Jan. 18,            1990, now issued U.S. Pat. No. 5,052,020; and        -   b. PCT application Serial No. PCT/US90/03282 (Attorney            Docket Nos. 91 P 392 & DN36767X-PCT), by Koenck et al.,            filed Jun. 7, 1990, now abandoned, which claims priority            from two applications:            -   1) U.S. application Ser. No. 07/364,594 (Attorney Docket                Nos. 91 P 859 & DN36808X), by Cargin et al., filed Jun.                7, 1989, now abandoned, which is itself a                continuation-in-part of U.S. application Ser. No.                07/339,330 (Attorney Docket Nos. 91 P 856 & DN36808), by                Cargin et al., filed Apr. 14, 1989, now abandoned; and            -   2) U.S. application Ser. No. 07/364,902 (Attorney Docket                Nos. 91 P 393 & DN36767), by Danielson et al., filed                Jun. 8, 1989, now abandoned.    -   3. U.S. application Ser. No. ______ (Attorney Docket Nos.        10126US03 & DN38000B), by Kinney et al., filed Aug. 17, 1993,        which is itself a continuation-in-part of U.S. application Ser.        No. 08/081,411 (Attorney Docket Nos. 10126US02 & DN38000A),        by P. Kinney, filed Jun. 22, 1993, which is in turn a        continuation-in-part of U.S. application Ser. No. 08/053,901        (Attorney Docket Nos. 10126US01 & DN38000), by Kenney et al.,        filed May 20, 1993, now abandoned.    -   4. U.S. application Ser. No. 08/097,462 (Attorney Docket Nos.        10222US01 & DN38017), by West et al., filed Jul. 26, 1993.    -   5. U.S. application Ser. No. 08/059,447 (Attorney Docket Nos.        10132US03 & DN37882XA), by R. Meier, filed May 7, 1993, which is        a continuation-in-part of U.S. application Ser. No. 08/056,827        (Attorney Docket Nos. 10127US02 & DN37882X), by R. Meier, filed        May 3, 1993, which is a Continuation application of U.S.        application Ser. No. 07/769,425 (Attorney Docket Nos. 91 P 668 &        DN37882), by Meier et al., filed Oct. 1, 1991, now abandoned.

INCORPORATION BY REFERENCE

The following applications are hereby incorporated herein by referencein their entirety and made part of this applications

-   -   1. U.S. application Ser. No. 07/898,908 (Attorney Docket Nos. 92        P 447 & DN36767XZAA), by Koenck et al., filed Jun. 12, 1992.    -   2. U.S. application Ser. No. 08/071,555 (Attorney Docket Nos.        10168US04 & DN36767XZX), by Koenck et al., filed Jun. 4, 1993.    -   3. U.S. application Ser. No. ______ (Attorney Docket Nos.        10126US03 & DN38000B), by Kinney et al., filed Aug. 17, 1993.    -   4. U.S. application Ser. No. 08/097,462 (Attorney Docket Nos.        10222US01 & DN38017), by West et al., filed Jul. 26, 1993.    -   5. U.S. application Ser. No. 08/059,447 (Attorney Docket Nos.        10132US03 & DN37882XA), by R. Meier, filed May 7, 1993.    -   6. U.S. application Ser. No. ______ (Attorney Docket Nos.        10092US04 & DN37998C), by R. Mahany, filed Aug. 3, 1993.

AUTHORIZATION PURSUANT TO 37 CFR 1.71 (d) (e)

A portion of the disclosure of this patent document contains materialwhich is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears in the Patent and TrademarkOffice patent file or records, but otherwise reserves all copyrightrights whatsoever.

BACKGROUND OF THE INVENTION

This invention relates generally to portable data collection andprocessing terminals for use in a Radio Frequency (RF) communicationnetwork, and, more specifically to portable terminals supporting avariety of RF transceivers and associated antenna systems. Additionally,this invention relates to methods in which a portable terminal gainsaccess to the RF communication network.

In particular, portable data processing terminals have taken anincreasingly significant role in business environments. For example,battery powered, hand-held data collection terminals are usedextensively for inventory control in warehousing and merchandisingoperations. Other uses of such terminals include invoicing, deliveryroute management, order taking and return control operations—as might befound in automobile rental operations.

In many business environments, portable data processing terminals oftenneed to communicate in real-time with other portable terminals,peripheral devices, work stations, and host computers. To meet suchcommunication needs, a variety of mixed hard-wired and wirelesscommunication networks with associated communication protocols have beendeveloped, each addressing the specific requirements of a given businessenvironment. In the process of such development, portable terminals haveundergone tailoring of both hardware and software to fully support aspecific communication network and associated protocol.

As a result of such tailoring, each type of portable data collectionterminal is generally only capable of operating in a single type ofbusiness environment. Tailoring also results in unreasonable additionalcosts associated with developing, manufacturing, documenting, etc., eachvariety of portable data collection terminals.

More specifically, each portable data collection terminal includes abuilt-in radio transceiver. The built-in transceiver operates pursuantto only one of a variety of types of RF (Radio Frequency) communicationcharacteristics, characteristics that are dictated per FCC (FederalCommunication Commission) specification.

The choice of the type of radio transceiver, i.e., the type of RFcommunication characteristics, to build-in is based on the nature of thebusiness environment. For example, a digital cellular radio might bechosen in a environment having great distances between the radio and thedestination transceiver. Similarly, data might be exchanged using asingle channel UHF (Ultra-High Frequency), direct-sequencespread-spectrum, or frequency-hopping spread-spectrum band. Each ofthese bands have particular characteristics which make them attractivefor a given business environment, and each generally requiring adifferent transceiver.

After choosing the appropriate radio transceiver, an appropriate antennamust also be selected. Each type of transceiver often requires adifferent type of antenna based on the corresponding RF communicationcharacteristics, the shape of the portable terminal, and the businessenvironment at issue.

Thus, there is need to provide a portable data collection terminalcapable of easily supporting any of the plurality of types of radiotransceivers and associated antennas, minimizing needed modifications tothe terminal's hardware and software design.

In addition, to support real-time access to a communication network,each portable data collection terminal needs to establish and maintainradio connectivity to the network. However, portable terminals must alsoaddress conflicting concerns of battery power conservation, i.e.,maintaining connectivity places a substantial load on battery power.Moreover, the mobile nature of portable terminals also presentsdifficulties in maintaining connectivity. It would therefore bedesirable to implement communication protocol techniques which addresspower saving and mobility concerns while providing virtually real-timeaccess to the communication link.

Thus, an object of the present invention is to provide a modularhardware and software radio design for a portable data collectionterminal which supports multiple types of radio transceivers andassociated antennas.

It is also an object of the present invention to provide for theselection of ones of a plurality modular radio transceivers for use by aportable data terminal, the selection of which addresses the specificconcerns of a given business environment.

Another object of the present invention is to provide for the selectionof ones of a plurality of modular radio transceivers for use by aportable data terminal, wherein each modular transceiver selectedisolates the data collection terminal from transceiver specificoperations by providing hardware and software control over suchfunctions.

A further object of the present invention is to provide a communicationprotocol which address power saving and mobility concerns whileproviding virtually real-time access to the communication link.

Another object of the present invention is to provide a communicationprotocol for use by a portable data collection terminal which minimizestransmission collisions while providing for virtually real-time accessto the communication network.

Another object of the present invention is to provide a communicationprotocol for use by a portable data collection terminal which eliminatesthe need for random number generation and random back-off techniques.

A further object of the present invention is to provide an improvedcomputer device apparatus for connecting a removable card type radio toa protected, interchangeable, environmentally sealed antenna which usescontacts located on the housing of the radio card.

An object of the present invention is to provide an improved antennaconnector for use with radio cards which can be inserted into variouscomputer devices.

An object of the present invention is to provide an antenna cap, for usewith computer devices utilizing radio cards, which is reliable,economical and easy to use.

A further object of the present invention is to provide an antenna capwhereby an appropriate antenna will be connected to a radio card byselectively positioning the antenna contacts on the radio card.

Another object of the present invention is to provide an antenna capwhereby a radio card may simultaneously connect to and utilize more thanone radio antenna, and where the radio card may contain more than onetype of radio transceiver.

A further object of the present invention is to provide an improvedantenna connector whereby an appropriate antenna(s) will be connected toa radio card by selectively positioning the antenna contacts on theradio card.

A further object of the present invention is to provide an improvedapparatus which utilizes only one set of contacts on a radio card ormodem card and uses a switching matrix to connect the radio card ormodem card to the appropriate antenna or telephone line.

Other objects, advantages, and novel features of the present inventionwill become apparent from the following detailed description of theinvention when considered in conjunction with the accompanying drawings.

SUMMARY OF THE INVENTION

These and other objects of the invention are achieved in a portable datacollection terminal comprising a first and second data processing unitas well as a radio transceiver selected from a plurality oftransceivers. The first processing unit is capable of operating at itsown set of communication software routines. Further, each of theplurality of radio transceivers has different operating characteristics.The second processing unit is capable of isolating the first processingunit from the differences in the operating characteristics of theplurality of radio transceivers.

In one embodiment of the portable data collection terminal, the firstprocessing unit is contained in a base module while the secondprocessing unit and the selected radio transceiver are located in acommunication module. In another embodiment, antennas are connected tothe base module, and the portable data collection terminal unit includesa means for selectively interconnecting one of the antennas to thecommunication module. In a further embodiment, a preinstalled antenna isconnected to the base module. The portable data collection terminalincludes an antenna connector capable of connecting a variety ofexternal antennas as well as a means for selectively interconnecting thepreinstalled antenna or the antenna connector to the selected radiotransceiver.

The objects of the invention are also achieved in a portable datacollection terminal that operates in a communication network having afirst and second subnetwork. The portable data collection terminalcomprises a base processing unit and a communication processor, as wellas a first and second radio transceiver selected from a plurality ofradio transceivers. The base processing unit is capable of operating atits own set of communication software routines. Further, each of theplurality of radio transceivers has different operating characteristics.The communication processor is capable of isolating the base processingunit from the differences in the operating characteristics of the firstand second radio transceivers.

In one embodiment, the base processing unit is contained in a basemodule of the portable data collection terminal. The data collectionterminal also has a communication module that contains the communicationprocessor and the first and second radio transceivers.

The objects of the invention are also achieved in a method used by asecond device for beginning a data exchange over an RF communicationlink with a polling device. (The polling device having an interpoll gaptime.) The method comprises identifying that an RF communication link isclear throughout a period which is at least as long as the interpoll gaptime and transmitting a request for poll frame. In one embodiment, themethod also includes generating a first pseudo-random time which is alsoat least as long as the interpoll tap time. The channel is then sensedfor a time substantially shorter than the first pseudo-random time. Suchsensing is repeated until the channel is detected as being busy, oruntil the channel is detected as being clear at every sense until thefirst pseudo-random time is reached. If the channel is busy, a secondpseudo-random time delay backs-off is executed and the process beginningat the generation of the first pseudo-random time is repeated. If thechannel is clear for the entire first pseudo-random time, a request forpoll is transmitted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic pictorial representation of a modular datacollection terminal unit to which the present invention applies andshowing schematically physical representation of modules of the datacollection terminal;

FIG. 1A is a schematic diagram of functional blocks for illustratingmajor functional elements of a base module and a respective data andcommunications module of a data terminal in accordance with the presentinvention;

FIGS. 1B and 1C are diagrams illustrating the modularity of the softwareprotocol stack used by the data terminal in accordance with the presentinvention;

FIG. 2 is a schematic diagram of functional interfaces among variousmodules of the data collection terminal shown in FIG. 1.

FIG. 3 is a schematic diagram of a control microprocessor, illustratingdata bus terminals for synchronous communications.

FIG. 4 is a sequencing diagram showing schematically occurrences of amodule-initiated communication sequence in accordance with features ofthe invention;

FIG. 5 is a further sequencing diagram illustrating schematicallyoccurrences of a controller-initiated communication in accordance withfeatures of the invention;

FIG. 6 is a schematic diagram of an alternate embodiment of theinvention showing major functional elements and their interaction with apower saving microprocessor control circuit in accordance with theinvention;

FIG. 7 is a schematic diagram showing typical, frequency related currentcharacteristics of a control microprocessor device of the circuit shownin FIG. 5;

FIG. 8 is a schematic diagram showing frequency related currentcharacteristics of an application microprocessor device of the circuitshown in FIG. 5;

FIG. 9 is a flow diagram showing a desired interaction of the twomicroprocessor devices in FIG. 5 in accordance with the invention;

FIG. 10 is a diagram illustrating a protocol stack used in the dataprocessing terminal of the present invention;

FIG. 11 is a diagram illustrating a local area communications network ofthe present invention;

FIG. 12 is a flow diagram illustrating another protocol embodiment usedby the data processing terminal of the present invention for gainingaccess to the channel;

FIG. 13 is a flow diagram illustrating an alternate protocol embodimentused by the data processing terminal of the present invention forchannel access which includes a retry counter;

FIG. 14 is a flow diagram illustrating an alternate protocol embodimentused by the data processing terminal of the present invention forchannel access which uses periodic SYNC messages in roamingimplementations;

FIG. 15 is a flow diagram illustrating another protocol embodiment usedby the data processing terminal of the present invention for channelaccess which includes both periodic SYNC messages and a retry counter;

FIG. 16 is a flow diagram illustrating a channel access protocol using apseudo-random number generator according to another embodiment of thepresent invention;

FIG. 17 is a diagram of the basic communication structure used in thechannel access protocol of the present invention;

FIG. 18 is a diagram illustrating an exemplary communication sequenceaccording to the channel access protocol of the present invention;

FIG. 19 is a diagram showing an exemplary communication exchange andillustrating channel access using channel reservation scheme;

FIG. 20 is a flow diagram illustrating channel access using the channelreservation scheme of FIG. 19;

FIG. 21 is a perspective view of a radio card and a corresponding portfor receiving the radio card built in accordance with the presentinvention;

FIG. 22 is a partial top plan view of a radio card and port forreceiving the radio card with the radio card completely inserted in theport;

FIG. 23 is a partial side elevational view taken along line 3-3 showingthe male/female pin connection of the radio card and the port of FIG.22;

FIG. 24 is a front view taken along line 4-4 showing the female pinconnections of the radio card of FIG. 21;

FIG. 25 is a perspective view of computer terminal showing the slot forreceiving the radio card;

FIG. 26 is front view taken along line 6-6 showing how a radio card tobe inserted into the slot of the computer terminal of FIG. 25;

FIG. 27 is a perspective view of another radio card and a correspondingport for receiving the radio card built in accordance with the presentinvention;

FIG. 28 is a front view of another computer terminal and end cap capableof receiving a radio card;

FIG. 29 is a top view taken along line 9-9 of the computer terminal ofFIG. 28;

FIG. 30 is a bottom view taken along line 10-10 of the computer terminalof FIG. 28 with the end cap removed;

FIG. 31 is a side elevation view taken along line 11-11 of the computerterminal of FIG. 28 with the slot for the radio card shown in dashedlines;

FIG. 32 is a partial top view taken along line 12-12 of the computerterminal of FIG. 31 showing the slot for receiving the radio card andthe antennas;

FIG. 33 is a partial top view of yet another embodiment of a computerterminal built in accordance with the present invention showing the useof a switching matrix;

FIG. 34 is a back view of a computer device and radio card built inaccordance with the present invention;

FIG. 35 is a side elevational view taken along line 2-2 of FIG. 34 ofthe computer device and radio card;

FIG. 36 is a partial top view taken along line 3-3 of FIG. 34 of thecomputer device;

FIG. 37 is a partial side elevational view of another computer devicebuilt in accordance with the present invention;

FIG. 38 is a top view taken along line 5-5 of FIG. 37 of the computerdevice showing the rubber cap inserted therein;

FIG. 39 is a partial vertical sectional view taken along line 6-6 ofFIG. 38 showing a radio antenna embedded within the rubber cap;

FIG. 40 is a partial vertical section view taken along line 7-7 of FIG.39 of the rubber cap;

FIG. 41 is a partial vertical sectional view of another embodiment ofthe present invention;

FIG. 42 is a partial vertical sectional view of still another embodimentof the present invention;

FIG. 43 is a partial back view taken along line 10-10 of FIG. 35 of thecomputer device;

FIG. 44 is a partial back view of still another embodiment built inaccordance with the present invention;

FIG. 45 is a partial horizontal sectional view taken along line 12-12 ofFIG. 44 of the band showing the shielded ribbon used to carry theantenna signals;

FIG. 46 is partial back view of a computer device of yet anotherembodiment of the present invention;

FIG. 47 is a diagram which illustrates the use of the portable dataterminal according to the present invention which utilizes a pluralityof radios to access different subnetworks of an overall communicationnetwork.

DETAILED DESCRIPTION OF THE INVENTION

Functional interconnections and power saving features of the presentinvention may be better understood from knowing how various buildingblocks or modules of a portable data collection terminal unit relate toeach other. FIG. 1 shows a schematic arrangement of various physicalmodules or components that become integrated into the portable dataterminal unit which is designated generally by the numeral 10. Hand-heldterminals are of generally rectangular, elongate shape for acceptedpractical user friendliness. Thus the modular terminal unit 10 desirablyhas an elongate, rectangular shape. An upper module 12 provides asensory or physical interface to an operator of the terminal unit 10.The module 12 is referred to as a keyboard and display module 12 andfeatures a keyboard 14 which may be a typical alphanumerical keyboard,including also function keys and cursor manipulation keys as part of anintegrated keyboard arrangement. The keyboard 14 may be, and desirablyis, a submodule in itself, inserted and mounted into a mounting frame 15of the keyboard and display module 12. In a typical manner, thedepression of molded keytops 16 generally closes electrical contacts ina lower contact plane (not visible) of the keyboard 14. The type ofkeyboard 14 is, however, not critical and not considered limiting to theinvention. The keyboard 14 being a selected one of a number of availablekeyboards is, however pertinent to the invention. For example, in oneapplication the keyboard 14 may be preferred to be a twenty or atwenty-four key keyboard. Such a keyboard 14 comprises comparatively fewkeytops 16, the locations and functions of which are more readilylearned and accepted by an operator. Such keyboards typically do nothave alphabetical key functions. Thus for many record keeping andmerchandising operations, the keyboard 14 having an array of twenty ortwenty-four keytops may be most desirable. In another operation, agreater number of keytops 16 may be required to display the letters ofthe alphabet, numbers, and to provide for the execution of variousfunctions. Thus, a keyboard 14 having an array of fifty-six keytops 16may be preferred. Numerous variations in the arrangement of the keytops16 within the array of the keyboard 14 are additionally possible.Mechanical or touch sensitive keytops 16 may be employed. In fact, touchsensitive keyboards which are known in the art, and typically involveprogramming and bi-directional feedback, may be improved byinterconnection features of the present invention which will becomeapparent from the detailed description as a whole.

The keyboard and display module 12 further includes an upper cavity 17wherein a display screen 18 is disposed. The display screen 18 ispreferably a state-of-the-art liquid crystal display, the liquid crystaldisplay (“LCD”) technology being well established in the art. Adot-addressable liquid crystal array screen 18 is ideal for “Userfriendliness” and versatility and permits the display of variousalphanumeric characters and graphic symbols, as well as Chinese orJapanese character symbols. Of course, dot-addressable graphicrepresentations are known to require a substantial level of dataprocessing and memory storage to permit the symbols to be displayed ormoved about on the display screen 18 with reasonable speed. Long delaysbetween the time that an operator pushes a keytop 16 to obtain data andthe time that the requested data are displayed is considered “userunfriendly” and is commercially undesirable. A display technology whichhas become a standard is referred to as VGA technology. VGA screens arecapable of fine gray scale or color resolutions. The display screen 18would be part of a selected display screen module 19 of a number ofavailable display screen modules.

FIG. 1A illustrates one embodiment of the data processing terminal ofthe present invention illustrating advantages in the modular designapproach. The terminal utilizes a microprocessor controlled datatransfer between the base module 201 and any of a number of data andcommunication modules which may include various radio transceivers suchas frequency-hopping or direct-sequence spread spectrum radios, UHF(Ultra-High Frequency) radios, etc. The terminal 10 and all of itscircuits, including those of attached modules, are powered by a powerpack module 23 as described herein.

Specifically, FIG. 1A shows a block diagram of functions of the basemodule 201 and a typical data and communications module designatedgenerally by the numeral 200. The base module 201 is operative inconjunction with a typical radio frequency transceiver provided by thedata and communication module 200, for example. The base module 201includes a typical keyboard module 202 interactively coupled to amicroprocessor 204. A preferred microprocessor is a 80C196KC devicewhich is a 16-bit microcontroller 205 with on-chip masked ROM, RAM andbuilt-in timers, ports, analog to digital converters and a serialinterface 206. Thus, the microprocessor functions as a microcontrollerand as an interface for communicating data and control signals to andfrom the base module 201. In addition to the on-chip memory capacity, anexternal ROM 207 and an external RAM 208 may be provided for additionaldata processing and communication capacity. Display controller anddriver circuits 209 may be multi-chip circuits or may be integrated intoa single device to drive the described LCD screen 210. A typical scannerinterface 215 is coupled to a 9-pin connector 216, such as the referredto D-subminiature connector which may couple a laser scanner or CCDscanner to the base module 201 for data collection.

The data and communication module 200 is of particular interest in thatan improved interfacing may be obtained by coupling communicationbetween the data and communication module 200 and the base module 201through a microprocessor 225, such as, for example an 80C51microprocessor circuit. Typical on board ROM allows the microprocessorto be programmed to interact with a number of devices in accordance withthe stored program. The microprocessor interacts with an interfacecircuit 226 which may be an analog or mixed analog and digital interfacecircuit. The program for interacting with the interface circuit 226 mayalso be stored within an on board ROM. The interface circuit 226 iscoupled to a transceiver module 228. The microprocessor 225 may also becoupled directly to a data collection interface 229 to receive data froma scanner for reading any number of different bar codes or for providinginput data from other external sources. The operation of themicroprocessor 225 for coupling data to the base module 201 allowsvarious input patterns to be processed by any of specific operationalprotocols controlled by the microprocessor 225, such that the data inputfrom the data collection circuit can be made the same from any of anumber of devices. Also, with respect to the operation of thetransceiver, the program for operating the microprocessor 225 mayinclude particular address codes for data retrieval and datacommunication via the transceiver. The data sent via a data and controlbus between the microprocessors 225 and 204 can emulate a uniform datatransfer protocol to the base module 201. The addition of themicroprocessor 225 in a data and communication module 200 thus increasesthe number of communications devices that may be represented by the datacommunication transceiver circuit or module.

The data and communication module 200 may be removed and replaced with anumber of other modules. In those modules, the transceiver 228 may be,for example, any RF radio, such as a spread spectrum, UHF, or cellulartransceiver. The commonality between all communication modules is themicroprocessor 225 and the associated communication protocol back to themicroprocessor 205 of the base module 201. In other words, the programfunction represented by the interface circuit 226 and interacting withthe microprocessor 225 permits the interactive control and data streambetween the base module 201 and the data and communication module 200 toappear the same to the base module 201 no matter how the module 200communicates.

The reference to the particular microprocessor circuits should not beconsidered limiting to the scope of the invention. The combination oftwo microprocessors interacting with each other, each controlling theenvironment of a respective one of two submodules such as the basemodule and the data and communication module permits an increased numberof different components and functions to be used within the data system.The data collection terminal unit of the present invention isparticularly designed for use in a mobile computer network. Such anetwork connects mobile interactive radio-equipped computers (such asthe terminal unit 10) to an infrastructure of stationary computerdevices.

Communication within the network is generally governed by softwarecontrol through a grouping of software routines. Together, the softwareroutines define an overall communication protocol for the network. Thesoftware groupings also define a stack of protocol layers; i.e., aprotocol stack. The protocol stack divides the overall communicationprotocol into hierarchical layers of functionality.

FIG. 18 illustrates one embodiment of the software protocol stack usedby the modular data collection terminal unit of the present invention.The protocol stack is split to illustrate that the functionality of thesoftware is divided between the base module 201 and the data andcommunication module 200. Specifically, the functionality of the upperlayers of the protocol stack (i.e., sessions layer 251, transport layer253, and network layer 255) is performed by the microprocessor 205 ofthe base module 201 while the functionality of the lower layers (i.e.,data link layer 257 and physical layer 259 is performed by themicroprocessor 225 of the data and communication module 200.

The sessions layer 251 performs general login functions, such asauthentication of passwords, etc.

The transport layer 253 provides end-to-end connectivity within a mobilecomputer network. It recovers from lost data packets, discards duplicatedata packets, and fragments and reassembles logical user messages.Essentially, the transport layer 253 provides a data pipeline betweenaccess points in terminal modes.

The network layer 255 provides end-to-end delivery of data packetswithin a mobile computer network. For example, if a spanning treenetwork offers the desired good network solution, the network layer 255would (1) organize nodes in the network into a spanning tree; (2) routedata packets along branches of the spanning tree; (3) provide a servicefor storing data packets for sleeping terminals (i.e. power management);(4) propagate lost terminal node information throughout the spanningtree; (5) maintain spanning tree links; (6) allocate and distributenetwork addresses; and (7) maintain and provide diagnostic networkstatistics.

The data link layer 257 controls access to the communication channel andis responsible for providing reliable transmission between any twodevices in the network on both wired and radio links.

The physical layer 259 performs radio modem functions and is thereforevery radio transceiver dependent.

As can be appreciated, the lower the level in the protocol stack, themore radio transceiver dependent the protocol becomes. Similarly, thelower the level, the more business environment specific the protocolbecomes. Thus, a good dividing line for the protocol layers that existin the communication module 200 is at the data link layer 257. This way,any communication module 200 supporting any type of radio transceivercan communicate with the common higher levels of protocol stack existingin the base module 201.

Alternatively, the dividing line might also be drawn at a higher level,for example, at the network layer 255, or at somewhere in between. Forexample, referring to FIG. 1C, a portion of the network layer whichaddresses the specific concerns of roaming portable terminals and powermanagement might be migrated into the communication module 200. Suchmigration permits the communication module 200 protocol substack to beable to communicate with other higher level protocol stacks which do notdirectly support such network layer functionality.

Further detail regarding mobile computer networks and the above protocolis found in attached Appendix A, a Masters Thesis entitled “MobileComputer Network Architecture” authored by Robert C. Meier, aco-inventor herein.

FIG. 1C illustrates the compatibility of the lower layers of theprotocol stack (i.e., that of the data and communication module 200 usedby the data collection terminal unit of the present invention with avariety of standard protocol stacks. Particularly, the protocol of thedata and communication module 200 is capable of interfacing with anypersonal computer (PC) based platforms that use a standard protocolstack. Such PC based platforms may include, for example, a NovellEthernet Network or TCP/IP. The network layer protocol associated withthe mobility of a terminal unit (i.e., specific spanning tree and powermanagement functionality), data link layer, and the physical link layeris managed by the microprocessor 225 of the data and communicationmodule 200. This protocol substack is stored in the interface circuit226. Similarly, the substack containing the sessions layer transportlayer and a majority of the network layer is stored in memory in thebase module 201.

In an alternate embodiment, FIG. 2 illustrates a schematic diagram offunctional interfaces among various modules of the data collectionterminal unit of FIG. 1. As will become more apparent below, theembodiment in FIG. 2 expands on the concept explained in reference toFIG. 1A of splitting up the hardware functionality and software protocollayers of the terminal unit 10 to enable ease of radio transceiversubstitution. FIG. 2 refers to a display screen module 20 which issimilar in function to display screen module 19 discussed above, yetwhich may include selected differences to illustrate the advantages ofthe modular concept in combination with other features of the presentinvention. Display screens may vary in size or resolution or both, suchthat options among a number of display screen modules 19 may be madeavailable to a potential user of the terminal unit 10. A display of anarray of (128 by 240) pixels of, for example, (0.25×0.25) millimeter isan example of what is considered to be a desirable display screenresolution. Another screen array size may be (64×192) pixels, forexample, of (0.35×0.50) millimeter per pixel.

The keyboard and display module 12 occupies most of the area of theterminal unit 10 which faces an operator when the terminal unit 10 isheld and operationally used by the operator. Assembled to an underside21 of the keyboard and display module 12 are preferably two majormodules of the terminal unit 10. A first module is what is referred toas the terminal module 22. Whereas the keyboard and display module 12 isthe major interface component between the operator and the terminal unit10, the terminal module 22 is a major functional component of theterminal unit 10 itself, as will become apparent from the descriptionherein. The terminal module 22 functionally controls the interaction ofthe various units or modules as described herein, and functionally isthe control unit of the terminal unit 10. The terminal module 22 housesfunctional submodules and microprocessor circuits. A significantcomponent is, of course, a power pack module 23. The power pack modulemay contain, for example, six AA type rechargeable cells which may bearranged in a convenient flat arrangement and fitted into a battery end24 of a housing 25 of the terminal module 22. The power pack module 23supplies the power to various modules of the terminal unit 10, thusproviding the capability for portable use of the terminal unit 10.

From the above description of potential choices of the type of displayon the display screen 18, and further choices among keyboardarrangements of the keyboard 14, different requirements for electronicsupport circuits are indicated. One of the requirements to support theeconomical changing of functions is a means to provide a ready change inprogrammability of microprocessor circuits. Some module selections ofthe terminal unit 10 require less memory usage and different operationalprotocols than others. In accordance with a preferred embodiment, amemory module 27 may be selected as one of a number of differentlyprogrammed memory modules 27. However, in addition to being differentlyprogrammed, an alternate memory module 28 may include a different memorysize (in cell numbers and in configuration). The terminal module 22 mayfurther include an exchangeable memory card 30. The memory card 30 maybe used to provide additional memory capacity as well as controlprograms for various desired functions of the various modules asdescribed herein. The memory card 30 is schematically shown as beinginsertable laterally into a slot 32 of the housing 25 of the terminalmodule 22. However, the shown physical arrangement is but one of anumber of equally desirable arrangements. At enclosed and sealedarrangement for the memory card 30 is desirable to protect modules ofthe terminal unit 10 from the environment.

A peripheral I/O module 34 is shown at a lower or inner end 35 (seeFIG. 1) of the terminal unit 10. The inner end 35 is typically pointedtoward an operator of the terminal unit 10, as the unit is held in theoperator's hand with the keyboard and display module 12 directed upwardtoward the operator. The I/O (Input-Output) module 34 may typicallyinclude externally of a housing 36 a standard RS-232 and RS-485connector 37. FIG. 1 also depicts a round communication connector 38.The peripheral I/O module 34 provides an interface between the terminalunit 10 and such diverse peripheral devices as “docks”. Docks may bebatch transfer devices for transferring accumulated data, batterycharging devices, or cables which may connect to a code scanner, forexample. An RS-232 interface is typically connected to a printer, forexample.

A serial I/O and scan connection module 41 may be attached at alongitudinally opposite outer end 40 (see FIG. 1) of the terminal unit10. The scan connection module 41 is a high speed serial datacommunication module 41 which provides for serial data to be received inhigh volume from a scanner for example. Scanner data are typicallyreceived in a high density data string and require significantprocessing. As will become apparent below, a direct communication linkto the data processing capability of the terminal unit 10 is providedthrough the scan connection module 41.

A further functional module is a communication module 44. Again inreference to FIG. 1, the communication module 44 may be disposedadjacent the terminal module 22 toward the outer end 40 of the terminalunit 100 The communication module 44 is selected from a group ofavailable communication modules of distinct functions. The selection ofone of the communication modules such as the communication module 44 inFIG. 1, may characterize or classify the operation of the terminal unit100 For example, a communication module 44 may have been selected from agroup of modules which include standard FM data radio transceivermodules, spread spectrum radio transceiver modules, modem communicationmodules, scanner device modules, or other data input devices. FIG. 2shows a communication module 45 as an alternate to the physicalrepresentation of the communication module 44 shown in FIG. 1 toindicate a diversity of modules available for substitution. In furtherreference to FIG. 1, the communication module 44 is shown as having anantenna 46, indicating the selection being a transceiver unit for radiofrequency real time communication with a data system. Such a data systemtypically includes a further transceiver station, not shown, with whichthe transceiver module communicates. The operator of the terminal unit10 also constitutes a second end of a communication link that isestablished by the operator's manipulation of the keyboard 14 and by theoperator's visual perception and recognition of the data displayed onthe display screen 18.

Referring now to FIG. 2, a functional schematic diagram of a combinationof the physical modules discussed with respect to FIG. 1, or ofalternate equivalents of the modules in FIG. 1, is shown. The moduleswith respect to which preferred physical positioning was discussed inreference to FIG. 1 are now shown functionally related in FIG. 2. It isto be noted that the schematic representation refers to functional orcommunication rather than electrical connections. The power pack 23 istypically coupled to power all electrically driven circuits of theterminal unit 100 The power pack 23 is functionally and physicallycoupled to the terminal module 22. While electrical power is distributedfrom the power pack 23 to all electrically powered or controlled modulesof the terminal unit, the remaining power of the power pack is actuallymonitored by a function of the terminal module 22. The power pack 23 asthe sole portable power source for the terminal unit 10 would, but forpower saving provisions, experience a significant power drain during theoperation of the terminal unit 10.

Power savings are implemented by selectively using circuit functions asthey are needed. Accordingly, the terminal module includes preferablyfirst and second microprocessors 48 and 49, respectively. The firstmicroprocessor 48 is a data processing device and is also referred toherein as an application processor 48. The application processor may beany of a number of available microprocessors available. Desirably theapplication microprocessor 48 has the capability of processing data withgreater word length or word width than the second processor 49. The termword width refers to the number of data bits that are capable ofsimultaneously being processed, retrieved or stored. The applicationprocessor 48 is therefore one capable, for example, of processing a16-bit or a 32-bit data word. The processing speed and clocking rate ofthe application processor 48 would desirably exceed that of the secondmicroprocessor 49. At present, the more powerful microprocessors, suchas the microprocessor 48, have higher power requirements than the secondmicroprocessor 49. However, even with the higher power requirementduring operation, power savings may be achieved by providing a reststate at which the microprocessor 48 is not clocked and thusdeactivated.

The second microprocessor 49 is also referred to as a control processor49. The second microprocessor controls the operation of the terminalmodule 22 and controls communication within the terminal module as wellas among the various other modules of the terminal unit 10. The controlprocessor 49 requires less power for operation than the applicationprocessor 48 for reasons that will become apparent. Control is anongoing function. Because the operational speed of the control processor49 is comparatively slower than that of the application processor 48,the operational power consumption of the control processor 49 is alsolower than that of the application processor 48. The control processor49 may be a Hitachi H8/330 type microprocessor device. The HitachiH8/330 processor features on-board memory which is convenient for itsintended operation as will be seen in reference to its operational modesas set forth herein. The H8 type processor is an 8-bit processor,capable of processing data in an 8-bit word length. However, the controlprocessor 49 need not be an 8-bit processor. In general, the word widthprocessing capacity of the control processor 49 should be chosen to berelatively less than that of the application processor 48. The controlprocessor 49 does not require the processing speed that is desirable forthe application processor 48, and, processors with relatively low wordwidth processing capacity (considering processors in general) requireless processing power. It should be understood, however, that thespecification of any particular device, such as the Hitachi H8-typemicroprocessor for the control processor 49, is for illustrativepurposes only. The features and desired functions of the invention willbe helpful to one skilled in the art to select any of a number ofacceptable devices to function in the desired manner as describedherein.

FIG. 3 shows a schematic block representative of signal terminals of thecontrol microprocessor 49 which are pertinent to the preferred mode ofimplementing the present invention. In describing the significant signaland data terminals, a bar above a designation indicates that a lowsignal is active. Herein, the inverse or signal low active state isdescribed with an “N” preceding the letter name at the respective signalterm. To communicate among the various described modules, four signalleads of the control processor 49 define the leads of a communicationbus 50 referred to herein as “MBUS”. The MBUS 50 is a high speedsynchronous serial data signal bus which may, and preferably does,operate at a signal rate of 500 kilo bits per second. The high speeddata bus provides reliability advantages explained below. In a modularstructure in which the modules are readily disconnected and reconnectedto permit convenient changes during the manufacture of the finalproduct, may reduce the reliability of the terminal unit 10. Whenreliability is decreased with each additionally coupled module, theadvantages of modular structure are quickly dissipated. Compared totypical parallel data buses used to link components of electronicproducts or systems, the present system architecture of the modularterminal unit 10 requires significantly fewer contacts to interconnectthe various modules. With fewer signal lines to manage, it becomes morefeasible to protect each line from noise and interference effects byusing well known shielding, impedance reduction and terminationtechniques thereby increasing the reliability of the terminal unit 10.As a result, the present invention is typically more reliable thanmodular systems with conventional parallel data transfer, due to thereduction in the interconnections among the various modules. FIG. 3shows four signal terminals which constitute the MBUS concept. “MCLK” isthe clocking signal which synchronizes the modular counterparts of thecontrol processor 49. The clocking signal provides for a bit rate of 500kilo bits per-second. The terminal labeled “MTXD” transfers data fromthe control processor onto the MBUS 50. The terminal labeled MRXDreceives data from other modules over the MBUS 50. The low signal active“NMATT” is a control signal line which indicates that data will becommunicated over the MBUS 50. These four lines effectively permit thevarious modules to communicate among each other. A number of signalcontention protocols are available to resolve potential collisions indata communication. It should be understood that any standard signalcontention protocol may be modified if so desired to assign specificpriorities for communication among the modules. For example, datareceived from a scanning operation may be accepted and processed on apriority basis. Keystroke inputs from the keyboard and display module 12may be given priority over data flow from the communication module 45.Similarly, data messages received via radio transmission from anexternal master unit (not shown) may be given priority. Program alteringinstructions may be embedded within the message which affect futureoperations of the terminal unit 10.

Further with respect to FIG. 3, corresponding data lines interfacingwith the application processor 48 are indicated as parallel signal linesDB0-7 and data lines A0-3. Data communication and control proceduresbetween the control microprocessor 49 and the application processor 48are further described with respect to alternate embodiments.

Referring again to FIG. 2, the application processor 48 is coupled to anasynchronous device or “UAR/T” function 51 with an output coupled to aserial port 52 of the serial I/O scan connection module 41. The serialI/O scan connection module 41 further includes a scan port 53 whichlinks to the control processor 49 to communicate control signals, suchas scan trigger signals, for example. The application processor 48 isfurther coupled to a VGA adapter circuit or driver 54 for driving thedisplay screen 20. The display screen function is processor intensive.Data processing operations are, therefore, managed directly through theapplication processor 48. The data processing operations performed bythe application processor 48 are in most instances memory-usageintensive. Consequently, the application processor 48 is linked by aconventional data bus 55 directly to the memory module 28. The memorymodule 28 is shown as including representative data storage functions orcircuits including a 16-bit word width system FLASH-programmable memory56, a typical 16-bit word width random access memory 57 (“RAM”), andadditional application FLASH-programmable memory 58, also preferably16-bit word width. The 16-bit word width storage devices 56, 57 and 58are preferred in conjunction with a 16-bit microprocessor device.Presently preferred 16-bit microprocessors are a Chips and TechnologiesF8680 device or an Advanced Micro Devices 386SXLV processor. Theselection of other processors for the microprocessor 48 may requiredifferent types of memory devices or different word width or storagecapacities than those described above.

The peripheral I/O module 34 may, as discussed with respect to FIG. 1,include standard connectors for coupling the module 34 to an externaldevice. A particular device 59 may be a portable printer device, asshown in the function block 59 of FIG. 2, which may be mounted orcoupled directly to the terminal unit 10. The peripheral I/O device,whether it is a printer or a reader or other data input or outputdevice, would functionally include a microprocessor 60. Themicroprocessor 60 is chosen to interact with the MBUS system. Themicroprocessor 60 is coupled in each described element to function as aterminal element, which is an interface communicatively coupling therespective logic circuits of the module to the MBUS. The microprocessor60 receives control codes via the MBUS 50 and responds by activating orde-activating the power circuits of the respective module, orconditioning the module to receive or transmit data.

The communication module 45, which may be a modem or any of a number ofavailable radio frequency transceiver modules, also includes acompatible microprocessor 60 which interfaces with a respectivecommunication device 61 of the module 45. The communication device 61may be a modem or transceiver device, for example. To be compatible withthe MBUS data format of the other described modules. The keyboard anddisplay module 12 also preferably includes its own interfacingmicroprocessor device 60. The keyboard and display microprocessor 60 iscoupled to control various functions which are directly associated withthe keyboard and display module 12. A particular function which may beconveniently controlled via the MBUS 50 and the respective controlprocessors 49 and 60 is a backlight drive 62 for the display screen 20.Another function is a buzzer 63. The buzzer 63 may be activated tosignal an incorrect key depression by an operator. The buzzer 63 mayfurther be used to alert an operator when a charge and power controlcircuit 64 detects that the power pack 23 has become discharged and abackup battery 65 is being engaged, giving a user time to recharge orreplace battery pack 23. The power control 64 may function to shut downthe terminal unit 10 from further operation until the power pack hasbeen recharged. In a preferred embodiment, power from the backup battery65 would be maintained on the control processor to permit it todetermine when power from the power pack 23 has been restored. Theprocessor 60 of the keyboard and display module 12 may also controlother input or output devices that may be coupled to the keyboard anddisplay module 12. For example, a pen 66 may be coupled to the keyboardand display module 12 for use in connection with a pen stylus sensitivekeyboard module 14 or in connection with a pen stylus sensitive displayscreen 20. In this latter instance, the display screen module 20 becomesan input device in addition to being an output device.

The application processor 48 and the control processor 49 are preferablycontrolled through a timing Application Specific Integrated Circuit 67(“clock control ASIC”). The clock control circuit 67 may be driven froma single clock signal which is then divided to provide respectivelydifferent clocking rates to each of the processors 48 and 49. Theimplementation of the timing circuit 67 in a single circuit function ismore efficient and provides synchronization among the components andmodules. A second clock signal for implementing a real time clock mayalso be provided.

In addition to providing better reliability as discussed above, the MGUS50 also provides more compact physical routing of cables among themodules. Furthermore, control of the functions of the various describedmodules via the MBUS 50 provides power savings, as will be describedmore fully below in reference to FIGS. 4 and 5. To conserve power andprolong the operational time of the terminal unit 10 between changes orrecharges of the power pack 23, the control processor 49 and the relatedMBUS module processors 60 place any module which is not in active useinto dormant state.

The MBUS 50 communicatively interconnects the modules of the terminalunit 10, such as the peripheral I/O module 34, the communication module45, the keyboard and display module 12 and the terminal module 22. Othermodules that may be included in the active communication network of theMBUS 50 may simply be added as described herein. For each module, one ofthe microprocessors 60, having the data terminals of the microprocessor49 shown in FIG. 3, namely MOLK, MTXD, MRXD and NMATT are coupled to therespective lines of the MBUS 50 to become part of the internalcommunication network of the terminal unit 10. The microprocessors 49and 60 constitute the terminal elements of the communication networkrepresented by the MBUS 50. For each module, the respectivemicroprocessor 60, though it may be physically identical to the controlmicroprocessor 49, functions as a subservient processor to the controlprocessor 49. The microprocessors 60 become a communication interfacebetween the MBUS 50 and the functional circuits of the respectivemodule, whether the module is the communication module 45, the keyboardand display module 12 or the peripheral I/O module 34. Inputs from therespective module are accepted by the processor 60. An H8/330microprocessor includes internal memory for receiving and temporarilystoring data communications. Programmable ROM on the H8/330 permitinstructions to be stored which particularly configure themicroprocessor as a module processor 60. The interface operation of themicroprocessor differs from the controlling operation of the controlprocessor 49 as shown below in reference to FIGS. 4 and 5.

A normal state of the microprocessors 49 and 60 is a sub-active ordormant state. In this state, the module processors 60 and the controlprocessor 49 are clocked at a power saving “slow” clocking speed. Thesub-active or dormant operational state permits the module processors 60and the control processor 49 to execute certain long-interval controlfunctions. For example, the keyboard and display screen processor 60monitors the keyboard in order to sense a keytop depression while thecontrol processor 49 maintains the charge and power control circuit 64in order to sense a low battery signal. Upon occurrence of an eventwhich that affects the operation of any typical communication functionthat is driven over the MBUS 50, all modules and the control processorare placed into a fully activated mode. The control processor 49queries, directs and controls communication over the MBUS 50. Forexample, FIG. 4 shows an activation cycle of the MBUS 50 which isinitiated by one of described modules other than the terminal module 22,i.e., from one of the processors 60. The respective processor 60 drivesthe NMATT line of the MBUS 50 into a low signal state. The low state ofthe NMATT line activates all processors 60 to receive an inquiry orinstructions. At T1 in FIG. 4 all modules have been placed into theactive state. During the time interval T1 to T2 the control processorsends a query or polls the activated modules over the MTXD line which isreserved for transmissions originating from the terminal module 22,i.e., from the control processor 49. The query would typically containat least one byte of data, the quantitative translation of the byte ofdata indicating to the processors 60 that it is a query in response toone of the module processors 60 having driven the NMATT line to a lowstate. The query shown at 70 signals the processor 60 to transmit itsdata message over the MRXD line of the MBUS 50. At the onset of the datatransmission 72 from the respective communicating module processor 60,the NMATT line is restored to a high state, placing all other modulesback into the dormant condition. As shown in FIG. 4, the datacommunication may proceed for a variable length of time past the timestate T2 at which the NMATT line has returned to a high state. Upontermination of data communication from the respective module processor60 to the control processor 49, the control processor 49 sends a message73 confirming correct receipt of the data message (at T3), Again theconfirming data message contains at least one byte of information, thedecoding of which would either indicate an error code or signal thecorrect receipt of the data message. At that time (at T3), thecommunicating module processor 60 and the control processor 49 alsoassume the power saving dormant state.

FIG. 5 describes a very similar event in which the control processor 49drives the NMATT line to a low state. Again, all processors 60 assume anactive state and all processors 60 receive a communication 75 oftypically at least one byte of information from the control processor 49during the time interval between T1 and T2. The information 75 containsan address of the module to which a data message from the controlprocessor 49 will be directed. The respective module processoracknowledges its understanding of the address by a responding message 76which may be translated by the control processor 49. In response to thereceipt of the message the control processor releases the NMATT line,which assumes its normal high state and places all non-affected moduleprocessors 60 again into a dormant state. The control processor 49 thentransmits its data message as indicated at 77 to the respective,previously addressed module processor 600 At the conclusion of thecommunication 77 from the control processor 49, the respective moduleprocessor acknowledges receipt of the communication 77 by its response78. Once it is interpreted from the response 78 that the communication77 has been received correctly, both the control processor 49 and therespective module processor 60 assume their dormant states. It is to benoted that the respective data messages shown in FIGS. 4 and 5 indicatedurations of data messages. It is to be understood that the high and lowstates of other than the NMATT line indicate a time interval duringwhich a great number of high or low states in synchronous time slots aretransmitted essentially at the bit rate of 500 kilo bits per second.This bit rate may include start and stop intervals.

In the described communication events, power consumption by the terminalunit 10 is minimized by providing for a quasi dormant state forsubstantially all functions of the various modules, such that electricalpower is used in pulses during the described query states and only inspurts by certain modules during real time performances. The powersaving features in communication from and to the various modules isfurther present in implementing highly power intensive data processingoperations in the terminal module 22.

Referring to FIG. 6, the schematic diagram illustrates an alternateembodiment of the present invention where major functional logic andcommunications elements are coupled to and interact with the applicationprocessor 48 and the control processor 49 in a power-conservingmicroprocessor circuit 80. The circuit 80 may control the operations of,or be functional in the operation of, the terminal unit 10. The terminalunit 10 may interact as described with one or more distinct functionalmodules including communication modules, such as a transceivercommunication module (“RADIO”) shown at 81. Because the terminal unit 10being portable, the physical circuits of the functional units or modulesshown in FIG. 6 would typically be powered by the power pack or battery23 (shown schematically in FIG. 2), which is illustratively included inthe power management function (“POWER CONTR”) 64. The microprocessoroperated control circuit 80 comprises a combination of the applicationmicroprocessor 48 and the control microprocessor 49. The circuit 80 canalso be two circuit portions that include specifically twomicroprocessor type subcircuits 48 and 49. Each of these subcircuits 48or 49 are separately functioning microprocessor blocks, modules orseparate microprocessor devices. In the preferred embodiment asdescribed herein the devices are respectively an application processor48 (“MP1”) and a control processor 49 (“MP2”). It is advantageous toperform data processing operations at a comparatively higher speed andwith a more powerful processor than is be desirable for relatively lesscomplex control functions.

The term data processing operation” is used herein in the sense ofmanipulating a series of binary codes according to programmedinstructions to arrive at a desired result. Because of the great numberof discrete binary operations required to perform many of the mostcommon data processing functions, higher processor speeds and morecomplex or powerful microprocessor circuits of those typically availableare more desirable for data processing operations.

In the now described embodiment, the application processor or dataprocessing device 48 may be an “Intel 80C188EB” device which is “16-Bit”microprocessor device, operated at a preferred speed of 9.2 megahertz(MHz). At such preferred clocking speed of 9.2 MHz, the powerconsumption or operating current consumed by the data processingmicroprocessor device 48 is approximately 55 milliamps (“mA”). Thecontrol processor 49 may be a “Hitachi H8/325” device which is an“8-Bit” microprocessor, operated at a speed of one-half of the speed ofthe data processing microprocessor 48, that is, 4.6 MHz. Because of thesmaller physical size of the control processor 49 and the slower,preferred clocking speed, the power consumption or current required bythe control processor 49 in its operational mode is only about 9 mA,that is less than one-fifth of the power consumed by the processor 48.In general, the control microprocessor circuit or the controlmicroprocessor 49 desirably operates at a slower and less powerconsuming speed than the application microprocessor circuit or theapplication microprocessor 48. A one-to-two speed ratio for driving therespective microprocessors 49 and 48 is preferably chosen because of thepower savings that are realized with respect to the portable terminalunit 10. Respective clocking circuits 82 and 83 (“CLCK 1 and CLCK 2”)are shown as providing respective timing signal ports coupled to therespective processors 48 and 49 to drive the processors at the desiredspeeds as described.

Also, a functional arrangement of the separate clocking circuits 82 and83 preferably may be replaced by the clock control circuit 67, as shownin FIG. 2. The clock control circuit 67 may be expanded in its functionto include an interface circuit function between the processors 48 and49 which includes data transfer as well as clocking functions. The clockcontrol circuit 67 would include in such coupling arrangement a typicaldivide-by-two timing circuit function. An original 9.2 MHz clockingsignal port and a signal port with the divided by two signal, comparableto the timing signal ports 82 and 83, would be coupled to the respectivetiming signal input ports of the processors 48 and 49, respectively, todrive the processors 48 and 49 at their respective speeds of 9.2 and 4.6MHz. As mentioned above, a second clock may be coupled to the clockcontrol circuit 67 to provide a real time clock.

As will become apparent from the further description, it is within thescope of the invention to integrate the distinct functions andoperational characteristics of the separately identified microprocessordevices 48 and 49 into a single integrated device. The resultingintegrated device 80 desirably includes respective interface functions,as further described herein, to implement the power-savingcharacteristics realized by the control circuit 80. Within suchintegrated device 80, the function of the application processor 48 isthen performed by a first microprocessor circuit block or circuitportion, and the function of the control processor 49 is performed by asecond microprocessor circuit block or circuit portion. These circuitblocks, portions or modules interact essentially in the same mannerwithin the circuit 80 as the currently used microprocessor devices 48and 49.

The control processor 49 may include in its commercial implementation,in addition to typical microprocessor registers and an arithmetic logicunit, such functional circuit blocks as ROM, RAM and communicationsports. These circuit blocks may also be included in any integrateddevice 80, or their functions may be supplied by peripheral devices. Asshown in FIG. 6, additional external memory 84 (“MEM”) may optionally beprovided to supplement such on-board memory 85 (“OM”), though fortypical operations as further described herein, the external memorydevice 84 is not required. According to one embodiment, datacommunication between the processors 48 and 49 occurs via an interfacecircuit that includes, for example, two 8-bit data registers or latchesdescribed in greater detail below in relation to FIG. 6. It should beunderstood, however, that the control processor 49 may have a direct businterface to enable direct coupling of the control processor 49 to theapplication processor 48. The coupled processors 48 and 49 are capableof bidirectionally passing data and control signals without thedescribed two 8-bit data registers or latches. Also, data latches aregenerally considered temporary data storage devices. Data from onedevice are latched into a respective data latch to be retrieved by asecond device. Although not preferred, it is contemplated that dual postmemory may be used as an alternative to the latches described below.

The clock control ASIC function 67 shown in FIG. 2 should be understoodto not only include the clocking signal coupling circuits to drive therespective application processor 48 and the control processor 49, but tofurther include the data interface or bus to permit the desiredbidirectional data and control code communication between the processors48 and 49 as further described herein. In further reference to FIG. 2,an integration of the processor devices 48 and 49 into a single devicedesirably may include the described function of the interface and clockcontrol circuit 67.

Referring again to FIG. 6, a first latch 86 (“LATCH 1”) of the twolatches is coupled through an 8-line parallel bus 87 to themicroprocessor 49, and through a similar bus 88 to the microprocessor48. Respective write and read lines 89 and 90 (“WRL1 and RDL2”) providecontrol or trigger signals for the processor 49 to write data into thefirst latch 86 and for the processor 48 to read data from the latch 86.A handshake or control signal line 91 (“CHAR AVAIL 1”) toggles between ahigh or “logic 1” to indicate to the processor 48 that data have beenread into the first latch 86 by the processor 49 and a “logic 0” tosignal that the processor has read or taken the data from the firstlatch 86. A second latch 92 (“LATCH 2”) similarly stores an 8-bit dataelement written into the second latch 92 by the processor 48 over asecond 8-bit write bus 93. A second read bus 94 transfers the dataelement stored in the second latch 92 from the latch to the secondprocessor 49. The control or trigger signals for writing into or readingfrom the second data latch 92 are provided over trigger lines 95 and 96(“WRL2 and RDL2”), respectively. A second handshake or control signalline 97 (“CHAR AVAIL 2”) coupled to the second latch 92 and to theprocessors 48 and 49 also toggles between high and low signal states toindicate in the high state the availability of data in the second latch92 and in the low state the completion of a read operation of the mostrecent data element by the control processor 49.

A control signal line 98 carries a control signal generated by thecontrol processor 49 which controls the duty cycle of the applicationprocessor 48. In reference to FIGS. 7 and 8, the current usage of thecontrol processor 49 ranges between a high of 9 mA in a typicaloperating mode and a low of about 7 mA in a typical “idle mode” at thepreferred frequency of 4.6 MHz, (See FIG. 7, graphs 100 and 101,respectively). It should be realized that even while “idle”, the controlprocessor maintains power to internal memory and performs typicalperiodic monitoring functions, such as, for example, sampling a keyboardcircuit 102 (“KB”) for a “Depressed Key” signal or routinely monitoringthe power management function 64 for a “Low Battery” indication.However, even when in the typical operational mode as indicated on thecurrent vs. frequency graph 100, the control processor uses only aboutone-sixth of the current used by the application processor 48 in itspreferred operational mode. On the other hand, when the applicationprocessor 48 is placed into an idle state (i.e., when it is not drivenby a clocking signal), the required maximum current rating is 0.1 mA, asshown by the high-low indicated values at the 9.2 MHz frequency mark atand below graph 103 in FIG. 8. Graph 103 indicates the typical operatingcurrent consumption of the application processor 48. It should be notedthat the application processor 48 could be deactivated by a completeelectrical shut down of the device. However, because of the lownon-clocked power or current draw of the application processor 48, theapplication processor function is preferably deactivated by eliminatingits clocking signal but maintaining the application processor 48 underDC bias. Removing the clocking signal from the application processorfunction achieves a desired power-down idle state while permitting thedevice 48 to be reactivated immediately by an appropriate “wake up”control signal from the control microprocessor 49.

Typical data processing operations performed by the applicationprocessor 48 require approximately 10 milliseconds of time and not morethan 20 milliseconds on the average of all operations which aretypically performed by the application processor 48. A more userfriendly and practical response time may be obtained from the terminalunit 10 (and less power is required) when the application processor 48performs substantially all data processing operations is subsequentlyimmediately deactivated than if a single alternative microprocessorcircuit were used operating at a higher rate and including sufficientcomputing capacity to perform all required functions in an appropriatelyshort time. The combination of the application processor 48 and thecontrol processor 49 amounts, only to an approximate increase in currentusage of typically about ten percent, and in the extreme of no more than20 percent, over the normal operating current level of the controlprocessor by itself. The power required by the application processor 48as controlled by the control processor 49 is about one fifth thatrequired by the control processor 49 itself when it is operatedcontinuously. However, the display speed and data manipulation speed ofthe terminal unit 10 essentially is the same as if the unit 10 werecontrolled by the more powerful application processor 48.

The operating current requirement for the application processor 48 isdirectly related to the number of actively switching elements in eachcomputational operation. Though having an interrupt function, thereferred to 80C188EB processor 48 does not include, in contrast to thecontrol processor 49, any internal memory devices. FIG. 6 consequentlyshows a data bus 55 of the processor 48 coupled to external memorydevices, such as the flash electrically erasable and programmableread-only memory 58 (“FLASH EPROM”), a read-only memory 104 (“ROM”) anda typical random access memory 57 (“RAM”). The ROM 104 is also thefunctional equivalent to the system FLASH memory 56. The data bus 55further couples the application processor directly to the display module20 (“LCD DISPLAY”) of the terminal unit 10. The display module 20 may bea dot addressable LCD graphic screen module, for example. A direct datatransfer by the high speed application processor 48 to the LCD screen ispreferred because of the substantial amounts of data handling orprocessing that is required in updating a particular screen. Forexample, even a small graphic screen display, such as a screen of 48×100pixels, requires that each of the pixels be updated on a continuousbasis. Typically control circuits, which are part of the data displayfunction of the module 20 and are not separately shown, and which may bespecific to a particular screen display, may routinely re-applycurrently displayed information dots in a cyclic refresh operation tothe already identified pixels of the screen. However, any screen update,such as a simple display line scrolling operation, requires that eachpixel of the screen be updated. To perform such updating of informationin a power efficient and prompt, user-friendly manner, a data processingoperation and the high speed passing of the updated data between the RAMmemory 57 and the data display 20 is accomplished during a shortoperational activation of the application processor 48. More dataprocessing with respect to the data display screen 20 may be requiredfor routine menu operations. Menu operations are particularly desirablefor such portable terminal units 10, in that the typical user may not bewell acquainted with computer terminals. Well defined menu operationswith a number of available menu levels may therefore significantlyincrease the usefulness of a terminal unit. In addition to requiring thenormal display screen update, menu operators also require data basesearing and data retrieval. The above-described operations the describedmicroprocessor circuit (i.e., with the selectively activated dataprocessing device 48 and the relatively smaller and slower controlprocessor 49) may be used to perform the menu operations.

Selective activation and deactivation of the microprocessor circuitportion implemented by the data processing device or applicationprocessor 48 also provides power savings when the operating speeds ofthe two processors 48 and 49 are the same. However, such power savingsdo not appear to be as great as those realized by the embodimentdescribed above.

The application processor 48 may also communicate with a high speedasynchronous communication interface 105 (“H.S. ASYNC INTRFCE”) tosupport facsimile or external display screen operations. In addition,the application processor 48 may communicate data to an RS-232/RS-485serial interface module 34 (“SERIAL INTERFACE”). However, it should berealized that certain communications operations, such as outgoingcommunications to a printer (not shown) for example, may occur under thecontrol of the control processor 49. Even when the application processor48 selects data for communication to a line printer, a typical printerspeed, except in a graphics mode, would be sufficiently slow to allowthe application processor 48 to operate in an intermittent, power savingmode. FIG. 6 consequently shows a second RS-232/RS-485 interface 106(“SERIAL INTRFCE”) coupled to a second data bus 107, which is furthercommunicatively coupled to the control processor 49 to support the abovedescribed data communication operation via the control processor 49.

The data bus 107 is further shown as being coupled via a bus extension108 directly to the application processor 48. The data bus extension 108is particularly provided for direct data communication between theapplication processor and a data scanner 109 (“SCAN”), which may, forexample, be a bar code reader. Because of the high rate at which dataare generated by the operation of a data scanner, the data are mostreliably received, processed and stored by the application processor 48.A scanning operation may consequently involve the operation of both theapplication processor 48 and the control processor 49. According to oneembodiment of the control circuit 80, the control processor 49 monitorsthe circuit function of the data scanner 109 to detect a control signalthat indicates the event of a scanner trigger depression. The scanningoperation results in a string of data appearing at the data bus 107 andthe associated data bus 108. Since the application processor 48 islikely to be idle at the time of the occurrence of a trigger signal, thecontrol processor places a “wake-up” signal on the control signal line98 to activate the application processor 48. The control processor 49further writes an 8-bit control character into the first latch 86. Uponcompletion of loading the control character into the data latch 86, thecontrol processor 49 places a “one” signal on the character availableline 91 to allow the application processor to read the control characterfrom the latch 86. The application processor reads and decodes thecontrol character in accordance with protocol instructions read from theROM memory 56, for example. In the example of a scanner triggerindication, the decoded control character signals the forthcoming stringof information to be received by the application processor 48 directlyfrom the scanner 109 over the data bus 108. Hence, in contrast to beingconditioned for the event of receiving data from the keyboard 49 or fromthe radio 81 (which data might preferably be received over the datalatch 86), the application processor would in the event of scannedincoming data be conditioned to read the “event data” as a string ofdata directly from the data bus 108. The term “event data” is used todescribe data relating to an event. Any time event data requiresprocessing, such event data would be routed to the application processor48 either directly, as described with respect to the scanner data, orbetween the two processors 48 and 49, such as by the circuit 67 or asimilar interface circuit. It should be understood that conditioning theapplication processor to receive a string of data directly via the bus108 need not be limited to the receipt of the scanner data. Suchconditioning is contemplated for any use of the terminal 10 whichrequires a high volume of data to be received and processed within ashort period of time. Upon completion of the scanning operation, atrigger release signal is loaded into the first latch and communicatedfrom the control processor 49 to the application processor 48. Uponreceipt of the signal and completion of any data processing operationsremaining as a result of the receipt of data via the data bus 108, theapplication processor instructs the control processor to apply a“wake-up” signal to the control signal line 98 upon occurrence of anyspecified event requiring processing of data. Thus, in one embodiment,the control processor 49 continues to control the application processor48 by transmitting control codes to selectively enable or disable theapplication processor 48 to directly receive data via the data bus 108.The receipt of data by the application processor 48 is referred to as“direct” data input, since the contemplated transfer of data via thedata latches 86 and 92 is bypassed.

FIG. 2 shows schematically one embodiment of electrical components of anexemplary terminal unit 10, and the interactive relationship of suchcomponents to the application processor 48 or the control processor 49.FIG. 2 shows schematically a plurality of electrical components whichare generally directly related to the functional elements discussed withrespect to FIG. 6. In the embodiment shown in FIG. 2, the applicationprocessor 48 directly controls the previously referred to high speedasynchronous communications interface 105 and the RS-232/485 standardsserial interface 34. The flash EPROM programmable read-only memory 58 ispreferred to have no less than 256K byte storage capacity. The flashEPROM may supplement or even replace standard ROM, such as memory 56,which is preferred to have at least a 512K byte storage capacity. TheROM, if used, provides typical and normally non-variable data processingprotocol instructions. Such ROM may include control instructions forstandard display updating routines as well as for other routines whichare typically implemented by standard keyboard instructions and whichpertain to typical data input and output commands.

The random access memory 56 may be a semi-permanent static RAM typecircuit. The memory may have a capacity of 512K bytes. The preferreddata storage capacity provides sufficient storage for an on-board database related to typical inventory or delivery route type information. Inview of the portability of the terminal unit 10, an unexpected loss ofbattery power may bring about a significant loss of information unlessthe stored data are protected from destruction until full battery poweris restored. For example, the terminal unit 10 may be returned at aninitial signal of “low battery” to a battery charger unit (not shown)for a recharging operation and any stored data may be transferred, evenwhile the battery 23 is being recharged, from the terminal unit 10 to ahost computer (not shown).

Display 20 may be a graphic display having an array of 48×100 pixels.Typical menu or special graphic screen data may be pre-established for aparticular terminal unit 10 or for an application group of such unitsand may be stored initially in the specific ROM 56 provided for theparticular unit or units 10. As previously discussed, the updating ofdisplayed data on the screen device 20 requires a significant amount ofdata processing. Typically, such data processing operations involveaccessing permanently stored screen display information, such as fromthe ROM or from the flash EPROM 58, the manipulation of suchinformation, and temporary storage of such manipulated information inthe random access memory 57. As shown in FIG. 2, the applicationprocessor 48 has direct functional control over the respective devicesresponsible for such data updating manipulations.

Contrast control is another function which is desirable in LCD displayscreen 20. In regards to FIG. 2, such a control may be integrallycoupled to the VGA adapter circuit 54. The contrast of the LCD displayscreen 20 is typically set and adjusted by an operator and is a matterof choice. The contrast may be adjusted, for example, by a typical keydepression or by a keyboard sequence given by an operator. Such controlinput executions are within the scope of operations of the controlprocessor 49. Thus, in response to an appropriate command from thekeyboard 102, the display contrast may be changed without activating theapplication processor 48. The contrast display may be controlled asindicated in FIG. 2 by the functional coupling of the keyboard circuit102 to the control processor 49, and the further coupling of theprocessor 48 to the contrast control circuit and then directly to theLCD display screen circuit 20.

In one embodiment, the LCD display screen 20 is equipped with abacklighting drive 62. Many warehouse operations, route deliveryoperations and even merchandising inventory operations are oftenperformed under sufficiently poor lighting conditions, thereby requiringa backlighting source to be supplied as a standard feature of the LCDdisplay screen 20. A backlight drive circuit 62 may be coupled throughthe MBUS 50 to the control processor 49. A backlight drive circuit foruse in conjunction with the exemplary terminal unit 10 is described incopending patent application by S. E. Koenck at al., Ser. No.07/776,059, filed on Oct. 11, 1991, which application is assigned to theassignee of the present application. Both the application processor 48and the control processor 49 may interact with the backlight drivecircuit 62 to provide for an operator controlled brightness controlsequence to be communicated to the backlight drive 62.

It should be realized that the control circuit 67 as an ASIC may alsoinclude, besides the timing function circuits for the real time clockand its functions, the clocking signals to each of the two processors 48and 49. The control circuit 67 may also provide the already describeddata communication functions between the application processor 48 andthe control processor 49, as represented in FIG. 6 by the two latchingcircuits 86 and 92. The function by the control processor 49 to activateor “wake up” the application processor for data processing operations isaccentuated in the representation of the “wake-up” feature by theseparate function line 98 in FIG. 2. In one contemplated embodiment, thecontrol circuit 67 may include integrally a switching circuit functionfor separately switching the application processor 48 off or on, asindicated in FIG. 9 by the function blocks “#1 OFF WAIT” and “#1 ON”. Aswitch in the integrated control circuit 67 may perform the switchingoperation by selectively interrupting and reestablishing the clockingsignal to the application processor 48. In another embodiment, theapplication processor 48 may provide a shutdown status signal to thecontrol processor 49 and shut itself down. The control processor 49subsequently returns the application processor 48 to an active stateupon occurrence of any event which requires the operation of theapplication processor 48. The process flow diagram of FIG. 9 generallydepicts operational procedures between the application processor 48 andthe control processor 49.

Further in reference to FIG. 2, a trigger control signal of the scannermodule 41 may be received by the control processor 49. However the dataflow from the scanner module 41 would be received directly by theapplication processor 48 for further processing and storage. Inputsignals which are received at speeds within the operational capabilityof the control processor 49 are received by and transferred through thecontrol processor 49. For example, key depression signals from thekeyboard 49 are generally received directly by the control processor 49.The keyboard for the terminal unit 10 referenced herein, as indicated inFIG. 2, may be a 6×8 key matrix. Because the real time selection of akey by an operator is slow in comparison to the processing speed of eventhe slower control processor, the interpretation of which key has beenselected may be made by the control processor 49. An “event” indicationcharacter communicated to the application processor 48 may alreadyreflect which of the available functions of a particular key has, beenselected. The preprocessing of slow occurring events limits theoperational periods of the application processor 48.

The control processor further controls an input to an audible alarmcircuit 63 (“BUZZER”). An audible alarm, a slow occurring event,generates a signal to alert an operator of an alarm condition or toindicate that a processing operation has been completed. For example,when the application processor 48 has received a string of data from thescanner module 41, and has further processed the received information toverify its correctness, the application processor 48 may communicate anacceptance code to the control processor 49 and be shut down fromfurther operation. The control processor will then routinely generate anaudible signal to alert the operator that the information has beenaccepted. Prior to communicating the acceptance code to the controlprocessor, the application processor may retrieve from its memory 57,for example, information relating to the bar code which has just beenread and accepted, and may compile an information screen displaying suchretrieved information to the operator prior to the deactivation of theapplication processor 48. Thus, by the time the operator is alerted bythe audible signal that the respective bar code has been read andaccepted, the pertinent information regarding the item represented bythe bar code is already displayed on the LCD display screen 20.

Other devices which may under direct control of the control processor 49are the radio 81 with its included radio interface (“RADIO INTERFACE”),and the power control circuit 64 (“CHARGE/POWER CONTROL”) of theterminal unit 10. A serial interface 34 (“RS-232/RS-485 SERIALINTERFACE”) may optionally be controlled by the control processor 49.Because of the power savings achieved by the described interactionbetween the application processor 48 and the control processor 49,various other devices or functions may be added to the general operationof the terminal unit 10 without unduly limiting its operational cycle.

The interaction between the control processor 49 and the applicationprocessor 48 is described in greater detail in reference to both FIGS. 2and 9. In general, as discussed above, the application processorperforms data processing operations, while the control processor 49performs input-output control operations, which include periodicmonitoring functions. The control processor 49 controls the activationor reactivation of the application processor 48. However, theapplication processor 48 processes the parameters and feeds to thecontrol processor 49 the respective instructions that control thecontrol processor 49. The application processor 48 is therefore,according to one embodiment, the one device which accesses theoperations protocol of the terminal unit 10 from either the ROM or theflash EPROM devices 56 or 58.

Referring now to FIG. 9, the depression of the power switch by anoperator, physically starts the terminal unit with a cold start at ablock 301. The turn-on starts the clocking signal and the reset of boththe control and application processors 48 and 49. The control processor49 may reset the application processor 48 at a block 303. The resetoperation starts the apparatus at a block 305 with an initializationsequence of communications between the application processor 48 and thecontrol processor 49. During the initialization, the applicationprocessor 48 retrieves from its program storage default values, such asfor a battery threshold value, and transfers the respective defaultvalue to the control processor 49 at a block 307. The control processorretains the default value and uses it in its further operations tooperate the power control circuit 64. Other initialization functions maybe performed, such as, for example, setting an initial contrast value onthe LCD screen display 20 at a block 309, and determining whether or notthe backlighting function is to be activated at a block 311. Theapplication processor 48 further may retrieve data from memory 56, 57 or58, and manipulate such data in a manner to indicate on the screen thatthe unit 10 is operational. Once the terminal unit 10 is initialized,the application processor 48 communicates to the control processor 49that it is assuming its rest state at a block 313, and is shut offpending the occurrence of an event.

Upon occurrence of an event at a block 315, such as a “battery lowindication” or the depression of a key by an operator, the controlprocessor 49 causes the application processor 48 to turn at a block 317.Typically the clock signal to the application processor 48 may beprovided by a control signal applied to the control device 67, or theapplication processor may be otherwise enabled, such as by an enablesignal applied to the control signal line 98. Upon being activated, theapplication processor 48 communicates with the control processor 49,such as via the interface circuit 24 as described above with respect toFIG. 6, to request at a block 319 data relevant to the type of eventthat has occurred. After receiving the respective communication from thecontrol processor 49, the application processor 48 tests the receivedinformation as to the type of event and proceeds to process data asrequired according to the program. FIG. 9 shows three typical events ofa large number of possible programmed events for which the applicationprocessor 48 may be activated. A typical key depression detected at ablock 321 may result in reading the value of the depressed key, at ablock 323, from the second data latch 92 as described with respect toFIG. 6, or from an equivalent register of the control device 67 in FIG.2. The information then results in the retrieval of data regarding theaddresses of pixels which will be changed to a logical “high” to depictthe information on the LCD display screen 20, at a block 325 therespective data being transferred to the respective circuit elements ofthe display screen 20. Thereafter, the application processorcommunicates to the control processor 49 that the instructions have beenexecuted and is shut down to await a further activation by an event atblock 315 and an instruction at block 317. The shutdown of theapplication processor 48 may be initiated either by the applicationprocessor 48 itself or by the control processor 49. Because the start-upor activation of the application processor 48 is initiated by thecontrol processor 49, it may be desirable to disable the applicationprocessor 48 through the control processor 49.

Another typical event for activating the application processor 48 may bethe detection of a low battery indication at a block 327 in response toa threshold value transferred by the application processor 48 to thecontrol processor 49 during the described start-up procedure. Theprotocol may require that the application processor 48 verify the lowbattery indication by providing its own comparison check at a block 329.Because of an impending shutdown due to a low battery indication, theapplication processor may complete any operation if the low batteryindication is still within tolerable limits or may suspend further dataprocessing because of risk of errors. The application processor mayfurther display a low battery indication on the LCD display screen 20 ata block 331 and then be shut off pending further event instruction asdescribed above.

Another type event may be a special function key instruction such as theindication that a menu operation has been selected at a block 333. Theapplication processor 48 proceeds to access a designated program routinecorresponding to the requested menu choice (“RETRIEVE MENU DATA”). Therespective program instructions are executed at a block 337, and theresult or completion of the routine is displayed on the LCD displayscreen 20 at a block 339. The displayed result may be preceded by arepetitive interactive data transfer between the application processor48 and the control processor 49, for example, when the menu choicerequires the transmission of displayed information to a host computer.In such an event the application processor 48 may transfer the displayedinformation character by character to the control processor 49. Thecontrol processor 49 in turn activates the radio interface and transfersthe information string to the radio interface to be transmitted inaccordance with the program instructions interpreted by the applicationprocessor 48. FIG. 9 shows an error trap at a block 341 to which theprogram instructions proceed if an event code is not recognized by theprogrammed event descriptions and resulting processing routines of theapplication processor 48 for the particular application of the terminalunit 10. The data processing operations performed by the applicationprocessor 48 generally require less than 10 milliseconds. Thus, on theaverage, operations including the processing of keystrokes and theassociated display manipulations require less than one fiftieth of theaverage operational period of the terminal unit 10. Substantial powersavings are consequently achieved by selectively de-activating andre-activating the application processor 48 for preprogrammed eventswhich require the execution of the respective data manipulations at aspeed not obtainable by the control processor 49.

Further in reference to FIG. 9, if none of the event tests recognize theparticular code supplied to the application processor 48, an event errortrap routine at block 341 is used to inform the operator of the errorcondition. Such a routine may, for example, instruct the operator toagain enter the most recently requested operation, and may include anaudible warning from the buzzer. Various changes in the describedcontrol sequence may be implemented. Certain routines may be implementedat the described slower speed by the control processor 49 directly,while the application processor 48 remains deactivated. Further, othermicroprocessor devices may be chosen for the application and controlprocessors, respectively. The described microprocessor devices areparticularly suitable for various operations that are performed by theterminal unit 10 in the above-referred to operations.

FIG. 10 illustrates a portion of the software protocol stack 401 thatruns on one of Norand Corporation's Portable Data Collection TerminalUnits, Model No TM 1100 (See attached APPENDICES B and C). Specifically,the MAC (Medium Access Control) layer 403 is responsible for providingreliable data transmission between the terminal unit and any other nodeor device in a mobile computer network. When a radio module (e.g.,Norand RM40 RF Module) is attached to the terminal unit and powered up,the MAC layer 403 and a Glue Logic Layer 405 are transferred to flashmemory in the radio module. The Glue Logic Layer 405 controls themicroprocessor in the radio module so that it is able to communicatewith the high speed main microprocessor of the terminal unit. Generally,the Bridge Layer 407 organizes the nodes or terminals of the mobilecomputer network into an optimal spanning, routes data between any twonodes or terminals in the network, and provides data package storage tofacilitate sleeping terminals. Appendix D provides an exemplary computerprogram listing of the software protocol stack 401 of FIG. 10 (BridgeLayer at pp. 1-33; MAC Layer at pp. 34-51; Glue Logic Layer at pp.52-59). These protocol layers are actually subgroupings of the protocolstacks illustrated in FIGS. 1B and 1C.

FIG. 11 shows an exemplary local area network (LAN) illustrating theroaming characteristics of the portable data collection terminals.Specifically, the illustrated ALN consists of a host computer 510,multiple access points 512, 514, 516 and a mobile computing device (MCD)518. The MCD 518, a portable data collection terminal, iscommunicatively coupled to the host computer 510 through an access point512. Although only one MCD, MCD 518, is shown typically a plurality ofMCDs would exist on the LAN. The MCD 518 communicates with the hostcomputer 510 through the access point 512 to which it is connected.

There are two situations in which the MCD 518 becomes disconnected fromthe network 501. First, where the MCD roams out of the range of oneaccess point, such as access point 512, into the range of another point,such as access point 514 as is shown by the dashed MCD 518 position.Alternatively, MCD 518 may enter a sleep mode where the radiotransceiver is powered down. The sleep mode provides for power savingsand is a desirable mode of operation is needed.

The MCD 518 and the access point 512 communicate in a structured manner,where the MCD 518 transmits a request-for-poll (RFP), the access point12 responds with a poll, the MCD 518 then transmits its data, and theaccess point 512 responds with an acknowledge (ACK) signal if the datamessage is finished or with another poll if there is still more data tobe transmitted. One data message from the MCD 18 to the access point 512may consist of several POLL-DATA sequences, where each DATA transmissionis a fragment of the entire data message. To initiate such communicationexchange, channel access protocols must be established.

FIG. 12 shows the process implemented by a mobile computing device whenit has a message to transmit to the host computer. A MCD wakes up at ablock 551 when it has a data message to transmit to the host computer.This wake-up can occur at any possible moment in time, i.e., a randomtime. After waking up, the MCD senses, at a block 553, thecommunications channel for a predetermined time, which is greater thanor equal to the maximum interpoll gap time. In this context, a maximuminterpoll gap time is defined as the maximum time between poll messagestransmitted from the access point to the MCD. This assures the MCD thata transmission from the access point to another MCD will occur withinthe sensing time if the channel is currently being used. If, at a block555, the channel is clear for the interpoll gap time, the MCD transmitsa RFP at a block 559, and the communications sequence begins. If, atblock 555, the channel is busy during the interpoll gap time, the MCDwaits a fixed time period at a block 557 and senses the channel at block553 as before.

Because the MCD wakes up at some random time to send data to the host,the probability of collision with the transmission of another MCD isextremely small. By sensing the channel for a fixed period of time andwaiting for a fixed period of time to retry transmission, the randomnature of transmission attempts is retained even after a busy channel issensed. For a collision to occur in this scenario, two MCDs would haveto wake up at the exact same moment in time, the probability of which isextremely small.

FIG. 13 shows a process similar to that of FIG. 12, except that a retrycounter implementation is used. Upon waking up to transmit at a block601, a MCD resets a retry counter to zero at a block 603, indicatingthat it is the first attempt to communicate on the channel. If, at block607, the channel is determined to be clear for the interpoll gap time,the MCD transmits an RFP at a block 609, and the communications sequencebegins. Each time the channel is sensed at a block 605 and is determinedto be busy at block 607, the retry counter is incremented at a block611. Once the retry counter reaches a threshold or predetermined MAXvalue at a block 613, the MCD stops trying to transmit and goes back tosleep for some relatively long period of time at a block 615 beforetrying to transmit again. If instead, the predetermined MAX value hasnot been reached at the block 613, the MCD may either wait or sleep fora predetermined or fixed time before trying to access the channel again.This channel access protocol allows a terminal, an MCD, to save power ifthe channel is heavily loaded by sleeping until the channel may be lessheavily loaded.

FIG. 14 shows the process implemented by a mobile computing device in aconfiguration where the MCD may be roaming between coverage areas anddisconnecting and reconnecting with different access points (as isillustrated in FIG. 11). In this situation, access points periodicallytransmit SYNC messages, so that a MCD which is roaming, or has beensleeping for an extended period of time, can connect to the proper basestation and synchronize its clock so that it knows when further SYNCmessages will occur. In this embodiment, therefore, after waking at ablock 651, the MCD listens to receive a SYNC message 653, 655 and 657before attempting to transmit on the communications channel, since itmay have awakened in the coverage area of a different access point.Thus, the amount of time, at a block 657, between wake-up and channelsensing or between a busy channel sense and a further channel senseshould be greater than or equal to the time between SYNC messages minusthe maximum interpoll gap time. This assures that a SYNC message will bereceived each time before the MCD attempts to sense the channel andtransmit. In addition, after receiving a sync signal, the MCD listensfor an interpoll gap time 659 to determine if the channel is clear, atblocks 659 and 661. If clear, the MCD transmits an RFP at a block 663.

FIG. 15 shows a process similar to that of FIG. 14, except that a retrycounter implementation is used to control the number of retry attempts.Upon waking up to transmit at a block 701, a MCD resets a retry counterto zero at a block 703, indicating that it is the first attempt tocommunicate on the channel. Each time the channel is sensed and isdetermined to be busy, the retry counter is incremented at a block 717.Once the retry counter reaches a predetermined MAX value at a block 719,the MCD stops trying to transmit and goes back to sleep at a block 723,for some relatively long period of time before trying to transmit again.This procedure allows a terminal to save power if the channel is heavilyloaded by sleeping until the channel may be less heavily loaded. Inaddition, if the channel is busy but the retry counter has not reachedthe MAX value, the MCD may either sleep or wait for a fixed period oftime at a block 721. Although a fixed period of time is desirable, arandom or pseudo-random back-off might also be used.

FIG. 16 is a flow diagram illustrating a channel access protocol using apseudo-random number generator according to another embodiment of thepresent invention. Upon waking up to transmit at a block 751, a MCDgenerates a pseudo-random number (e.g., 5-8 microseconds) at a block753. The MCD then senses the communication channel for a fewmicroseconds at a block 755. If the channel is determined to be clear ata block 757, the MCD determines whether the pseudo-random time periodhas expired at a block 757. If it has expired, the MCD transmits an RFPat a block 761, and the communications sequence begins. If thepseudo-random time period has not expired, the MCD again senses thecommunication channel for a few microseconds determined at a block 755to determine if the channel is clear at block 757, i.e., repeating theabove.

If the channel is determined to be busy at block 757, the MCD incrementsa retry counter at a block 763. If the retry counter has not reached apredetermined maximum value at a block 765, the MCD waits for apseudo-random time (e.g., 10 milliseconds) at a block 769 and thengenerates another pseudo-random number at block 753 and repeats theabove procedure. Once the retry counter reaches the predeterminedmaximum value, at block 765, the MCD quits trying to transmit and goesto sleep for a longer period of time at a block 767, before reawakeningat block 751 to retry the transmission.

FIG. 17 shows the basic communication structure in one embodiment of thepresent invention. Access points periodically transmit a series of SYNCmessages such as 809-813, while allowing time for communicationexchanges during the periods 815-819 between SYNC messages. In general,the SYNC message itself takes much less time than the amount of timeallocated for communication between SYNC messages. The time allocatedfor a SYNC message and for subsequent terminal communication (i.e.,until another SYNC message is transmitted) is depicted by periods803-807.

FIG. 18 shows a series of exemplary communication exchanges and channelaccess attempts where three MCDs are attempting to communicate in thesame general time frame. The three units attempting to communicate arereferred to as unit 1, unit 2, and unit 3. Unit 1 wakes up first at 831,in the first time interval 815. It must wait until it receives a SYNCmessage at 811, so it cannot attempt to transmit in time interval 815.Unit 2 is the next to wake up at 833, also in time interval 815. As withunit 1, unit 2 cannot transmit until a SYNC 811 is received, andtherefore cannot transmit in time interval 815.

After the timer set by unit 1 when it initially woke up expires, SYNCmessage 811 has been received by unit 1. Thus, unit 1 can listen to thecommunications channel at 841 for the maximum interpoll gap time,determine a clear channel, and begin its communications sequence at 843,all in this time interval 817. The timer initially set by unit 2 alsoexpires during time interval 817, and unit 2 has therefore received theSYNC message 811 and senses the communications channel at 847. However,unit 1 has not yet finished its transmission when unit 2 senses thechannel for the maximum interpoll gap time. Thus, unit 2 must defertransmission, and waits until time interval 819 to retry communication.

Meanwhile, also in time interval 817, unit 3 initially wakes up totransmit at 845. Unit 3 must wait for a SYNC before attempting totransmit, so it does not transmit in the time interval 817.

In time interval 819, after the SYNC message 813, unit 2 and unit 3 haveboth received a SYNC message and can sense the channel to attempttransmission. In this case, unit 3 listens to the channel at 861slightly before unit 2 senses the channel at 863, such that the channelis not busy when unit 2 begins to sense the channel. However, after unit3 has sensed the channel for the maximum interpoll gap time, it beginscommunication on the channel at 865. Unit 2 finishes listening to thechannel, also for the maximum interpoll gap time, after unit 3 has begunits communication, so unit 2 must defer communication. Unit 3 ends itstransmission at 867. Finally, after SYNC message 869 in time interval871, unit 2 senses an idle channel at 873 and transmits itscommunication to the access point at 875. Unit 2 ends its transmissionat 877. This sequence illustrates the interpoll gap time channel senseand the wait to transmit until after a SYNC message has been received.

The operation of the protocol of the present invention takes advantageof the inherently random wake-up time of a mobile computing device in alocal area communications network. Rather, than performing a randomback-off routine, the time of wake-up is used to ensure randomcommunications attempts, thereby preventing collisions due to manyterminals attempting to transmit immediately after a certain commonevent. This is done by preserving the random wake-up time, adding afixed amount of time to the time of wake-up in back-off procedures. Theprotocol of the present invention eliminates the need for random numbergeneration and the implementation of random back-off algorithms.

FIG. 19 is a timing graph illustrating an exemplary communicationexchange between a portable data terminal 901 and an access point 903.Upon determining that the channel is clear, the portable data terminal901 begins by transmitting an RFP (request for poll) frame 905. After aninterframe gap time 923, the access point 903 responds with a POLL frame907 to indicate to the portable data terminal 901 that it is availableto receive data. The portable data terminal 901 then sends a DATA frame909. The access point 903 acknowledges receipt of DATA frame 909 with aPOLL frame 911. The portable data terminal 901 then transmits DATA frame913 which indicates that data transmission is complete. The access point915 then transmits a CLEAR frame 915 to acknowledge receipt.

A channel reservation scheme is used to generally restrict channelaccess contention to RFP frames. Each frame transmitted during thecommunication exchange contains a channel reservation field (e.g., field931 in POLL 907) which may indicate either the number of outstandingframes or the amount of time required to transmit the outstandingframes.

This scheme enables other terminals attempting to access the busychannel to determine the actual amount of time during which they maysleep. Sleeping, i.e., or powering-down the radio for the duration ofthe channel reservation period (i.e., until the channel becomes clear)conserves battery power and aids in collision avoidance. Further,channel reservation may be implemented with the other channel accessembodiments discussed above during heavy communication traffic. In otherwords, channel reservation may supplement other channel access protocolswhen terminals using those protocols are continuously failing to gainaccess to the channel.

FIG. 20 is a flow diagram illustrating an embodiment of the channelaccess reservation scheme described above. A portable data terminal (ormobile computer device (“MCD”) wakes up to transmit data at a block 951.It then senses the channel for an interpoll gap time at a block 953before determining if the channel is clear at a block 955. If thechannel is clear, the portable data terminal transmits an RFP and thecommunication sequence begins (e.g., that shown in FIG. 19). If thechannel is busy, the portable data terminal listens for the channelreservation information on the channel at a block 959, and calculatesthe time that it should “sleep” and powers down at a block 961. At theend of the calculated sleep period, the portable data terminal wakes upto transmit at a block 963 and repeats the process by sensing thechannel for an interpoll gap time at block 953.

FIG. 21 shows a radio card 1110 and a receiving device 1111 built inaccordance with the present invention. The radio card 10 has a housing1113 inside which is a completely operation radio transceiver not shown.The receiving device 1111 in this embodiment of the present inventionuses a pair of opposed slots 1114 to receive and guide the incomingradio card 1110.

The radio card 1110 has a pair of antenna contacts 1115 positioned alongthe edge of the housing 1113. The receiving device 11 has acorresponding pair of antenna contacts 1116. As can be seen in FIG. 22,when the radio card 10 is inserted into the receiving device 1111 theantenna contacts 1115 on the radio card housing 1113 electricallyencounter the corresponding set of antenna contacts 1116 positioned onthe receiving device 1111. The antenna contacts 1116 on the receivingdevice 1111 are connected to an antenna cable 1118. The antenna cable1118 is in turn connected to an antenna not shown. Thus, when the radiocard 1110 is completely inserted into the receiving device 1111 theradio card 1110 automatically is connected to an antenna.

Referring again to FIG. 21, a radio card 1110 may have antenna contacts20, shown in dashed lines, located at different positions on the housing1113. Similarly, the receiving device 1111 may have several additionalpairs of antenna contacts 22. The additional pairs of antenna contacts22 on the receiving device 1113 can be used to allow access to severaldifferent antennas depending on the type and frequency of radiocommunication to be utilized by the radio card 1110. This access isaccomplished through additional antenna cables 1123 attached to theadditional contacts 11220 Thus, if the receiving device 1113 is part ofa hand held computer terminal which has more than one antenna attachedor built in, different pairs of contacts 1116 & 1122 can be used toallow access by the radio card to the different antennas depending uponthe frequency and range characteristics of each antenna. While a radiocard 1110 may only operate at one frequency and thereby only need oneantenna and therefore only have one pair of antenna contacts, thereceiving device 1111 still may have several pairs of antenna contacts1116 & 1122 all but one of which do not correspond to any pair of radiocard 1110 antenna contacts 1115.

Referring to FIGS. 23 and 24, when the radio card 10 is inserted intothe receiving device 1111 an interface between the radio card 1110 andthe receiving device 1111 is produced. The receiving device 1111 has aplurality of pins 1130 which form the male portion of a connector. Theradio card 1110 has a corresponding plurality of holes 1131 which formthe female portion of the connector and which engage the pins 1130. Thepins 1130 are connected to the computer terminal not shown by a seriesof electrical connections 1133 such as wires or electrical ribbon. Theholes 1131 in the radio card 1110 are electrically connected to theradio. When the pins 1130 are engaged in the holes 1131, electricalsignals can be exchanged between the radio card 1110 and the computerterminal. The electrical signals can be in the form of informationexchange, power supply or both.

The radio card 1110 of FIGS. 21-24 might also be a modem card not shown.In this embodiment, the connections would be the same as previouslydescribed with the only difference being that instead of the contactsconnecting the modem card to a radio antenna, the modem card would beconnected to a traditional telephone line, a cellular phone or anantenna for a cellular phone if the cellular phone was built within themodem card.

Referring to FIGS. 25 and 26, a computer terminal 1140 is shown built inaccordance with the present invention. The computer terminal 1140 has aslot 1142 for receiving a radio card 1144. The user of the computerterminal 1140 lifts up a flexible cover 1146 and inserts the radio card1144 into the slot 1142. The radio card 1144 engages with the computerterminal 1140 in a similar manner as described in FIGS. 21-24. The radiocard 1144 as a pair of antenna contacts 1148 which will engage with acorresponding pair of contacts inside the computer terminal 1140. Thepair of antenna contacts inside the computer terminal are connected to aradio antenna not shown.

Referring to FIG. 27, another embodiment of the present invention isshown. The radio card 1150 has two pairs of antenna contacts 1152 & 1153which will encounter respectively two pair of antenna contacts 1155 &not shown on the receiving device 1158. This embodiment accommodates aradio card 50 which can operate at two different frequencies whichrequire two different antennas. Standardization of antenna contactposition with antenna type is anticipated and covered by the presentinvention.

Referring to FIGS. 28-32, another embodiment of a computer terminal 1160built in accordance with the present invention is shown. The computerterminal 1160 has a removable end cap 1162. When the end cap 1162 isremoved, a slot 1160 is revealed which is used to receive a radio card1166. The slot 1164 in the computer terminal 1160 has three pairs ofantenna contacts 1167, 1168 and 1169 which are respectively connected tothree different radio antennas 1171, 1172 and 1173. The radio card 1166in this embodiment only has one pair of antenna contacts 1175. Thus,when the radio card 1166 is inserted into the slot 1164, the antennacontacts 1175 will match up to the antenna contacts 1167 and the radiowill utilize the internal antenna 1171. The external antenna 1173 andthe other internal antenna 1172 will not be used by this particularradio card 1166.

Referring now to FIG. 33, still another embodiment of a computerterminal 1180 built in accordance with the present invention is shown. Acommunication card 1185 is inserted into the computer terminal 1180. Thecard 1185 can either be a radio card or a modem card. The card 1185 hasa set or pair of contacts 1187 which encounter a set or pair of contacts1188 disposed on the receiving portion of the computer terminal 1180.The contacts 1188 are electrically connected to a switching matrix 1190,thus the radio card or modem card 1185 is electrically connected to theswitching matrix 1190.

The switching matrix 1190 is connected to a plurality of antennas 1192,1193 and 1194 and to a telephone jack 1195. The switching matrix 1190 isused to electrically and selectively connect the radio or modem card1185 to the appropriate antenna or to a telephone line. The switchingmatrix 1190 is controlled by the control microprocessor 1198 of thecomputer terminal 1180. The control microprocessor interrogates the card1185 to determine what kind of card it is and to determine what antennaor telephone connection it needs. The control microprocessor thensignals the switching matrix 1190 which connects the card 1185 to theappropriate antenna 1192, 1193 or 1194 or to the phone jack 1195.

FIGS. 34, 35 and 36 illustrate another embodiment wherein a computerdevice 1211 utilizes a radio card 1210 built in accordance with thepresent invention. The computer device 1211 has a housing 1212. Insidethe radio card 1210 is a completely operation radio transceiver notshown. The computer device 1211 has an opening 1214 in the housing 1212through which the radio card 1210 can be inserted into the computerdevice 1212. In the present embodiment of the invention, the receivingmeans for the computer device is a slot 1215.

When the radio card 1210 is inserted into the slot 1215 in the computerdevice 1211 an interface between the radio card 1210 and the computerdevice 1211 is produced. The computer device 1211 has a plurality ofpins not shown which form the male portion of a connector. The radiocard 1210 has a corresponding plurality of holes not shown which formthe female portion of the connector and which engage the pins. The pinsare connected internally and electrically to the computer device 1211 bya series of electrical connections such as wires or electrical ribbon.The holes in the radio card 1210 are electrically connected to the radiotransceiver. When the pins engage the holes, electrical signals can beexchanged between the radio transceiver inside the radio card 10 and thecomputer device 1211. The electrical signals can be in the form ofinformation exchange, power supply or both. The radio card 1210 includesantenna contacts 1217 to engage corresponding radio antenna contactsthat are connected to an appropriate antenna.

The computer device 1211 includes a cap 1220 which is designed tomatingly engage the opening 1215 in the housing 1212 of the computerdevice 1211 and thereby cover the slot 1215 used to receive the radiocard 1210. A flexible band 1222 attaches the cap 1222 to the housing1212 of the computer device 1211. One end of the band 1222 is connectedto the cap 1222 while the other end is attached to the housing 1212. Ahandle 1224 helps assist the removal of the cap 1220 from the housing1212 of the computer device 1211.

The cap 1220 is constructed of a closed cell foam material with high aircontent for low dielectric losses. Alternatively, a quality dielectricmaterial may be used to reduce the size of the antenna structure. Thecap 1220 when made of a foam material helps to protect the radio cardfrom the physical trauma typically associated with computer devices ofthese types. Additionally, as will be discussed in further detail below,the cap 1220 helps to environmentally seal the opening 1214 preventingharmful material from the outside such as dust or moisture from reachingthe radio card 1210 and helps to reduce the escape of electronic noisefrom the housing 1212 created by the radio card 1210 and computer device1211. As will be discussed below, a grounded metal shield covering aportion of the cap 1220 is used to reduce the escape of electronicnoise.

While the cap 1220 helps to seal the opening, protect the radio card1210 and hold the radio card in place, the primary function of the capis to provide the radio card 1210 access to an appropriate antenna orantennas. The connection of the radio card 1210 to the antenna is madethrough the cap 1220. The antenna or antennas can be embedded in the cap1220, embedded in the band 1222 or even attached to, mounted on, orembedded in the housing 1212 of the computer device 1211.

Referring now to FIGS. 37 and 38, a computer device 1230 built inaccordance with the present invention is shown with a cap 1234 engagedin the opening of the housing 1232 wherein a radio card can be inserted.A band 1236 is attached to both the cap 1234 and the housing 1232. Theband 1236 helps prevent the loss of the cap 1234 when the cap 1234 isnot engaged in the housing 1232 of the computer device 1230.

Referring now to FIGS. 39 and 40, the cap 1232 is shown engaged with thehousing 1232 of the computer device 1230. The cap 1234 includes anoutwardly extending lip 1236 which helps to environmentally seal theopening in the housing 1232 preventing harmful material from the outsidesuch as dust or moisture from reaching the radio card 1240 which hasbeen inserted into the computer device 1230. When the cap 1234 iscompletely inserted or fully engaged in the housing 1232, the lip 1235sealingly engages the housing 1232.

Embedded in the cap 1234 is an antenna 1250. The antenna 1250 isconnected to the radio card 1240 through contacts 1251 and 1252 disposedon the cap 1234 and contacts 1241 and 1242 disposed on the radio card1240. Contact 1252 is the ground contact for the antenna 1250 and isconnected to the end of the antenna 1250. Contact 1242 is the groundcontact for the radio card 1240. Contact 1251 is the signal contact andis connected to the antenna 1250 a short distance from the end of theantenna 1250. Contact 1241 is the signal contact for the radio card1240.

Contact 1251 and contact 1241 are disposed on the cap 1234 and the radiocard 1240, respectively, such that the contacts engage each other whenthe cap 1234 is inserted into or engaged with the housing 1232 of thecomputer device 1230. Similarly, contact 1252 and contact 1242 aredisposed on the cap 1234 and the radio card 1240, respectively, suchthat the contacts engage each other when the cap 1234 is inserted intoor engaged with the housing 1232 of the computer device 1230. Thecontacts shown in the present embodiment are of the metal button typewherein the connection is made when the two metal surfaces meet. Manyvariations of the contacts are possible including the use of male/femaleconnections and spring type contacts.

A shield 1248 is disposed around the bottom portion of the cap 1234 andis used to reduce the escape of electronic noise. Typically in computerdevices of this type, the inside of the housing of the computer deviceis shielded. Additionally, the area immediately surrounding the radiodevice such as a radio card may also be shielded. By shielding the cap1234, the integrity of the housing and radio shields are not breached bythe opening used to insert and remove the radio card. The shield 1248 isconnected to the antenna ground contact 1252 on the cap 1234. A hole1259 in the shield 1248 allows the signal contacts 1251 and 1241 toengage without being grounded.

Referring now to FIG. 41, the cap 1234 is shown embedded within whichare two antennas 1260 and 1262 designed to receive and transmitdifferent radio frequency signals. The first antenna 60 and the secondantenna 1262 are both connected to a common ground contact 1267 which isconnected to the shield and which engages the ground contact 1277 on theradio card 1270. The first antenna 1260 is connected to a first signalcontact 1265 and is disposed on the cap 1234 to engage a first signalcontact 1275 disposed on the radio card 1270. Similarly, the secondantenna 1262 is connected to a second signal contact 1266 and isdisposed on the cap 1234 to engage a second signal contact 1276 disposedon the radio card 1270. Thus the radio card 1270 will use a signal viacontact 1275 or via contact 1276 depending upon which antenna it wouldlike to use. Which antenna it would like to use is dependent upon thedesired frequency upon which it want to transmit and receive.

The radio card 1270 as shown has three contacts 1275, 1276 and 1277.However, if the radio transceiver in the radio card 1270 is designedsuch that it would only be able to transmit and receive signals whichcorrespond to the first antenna 1260, then it would not need to havecontact 1276 and it could be left off. Similarly, if the radio card 1270were only going to use second antenna 1262 then contact 1275 could beomitted. Thus, standardizing contact position with respect to antennatype allows for flexibility in cap usage with various radio cards suchthat only appropriate antennas will be connected to the radio card.

Referring to FIG. 42, two antennas 1280 and 1282 are embedded in the cap1234. In this embodiment built in accordance with the present invention,the two antennas 1280 and 1282 not only share a common ground contact 86which engages the ground contact 1296 of the radio card 1290, but theyalso share a common signal contact 1285 which engages the signal contact1295 on the radio card 1290. Thus, both antennas receive and transmitsignals using the same two contacts; This embodiment requires a radiocard 1290 which can filter the different signals and thus use the signalfrom the desired antenna while ignoring the signals which arrive via theother antenna.

Referring to FIG. 43, a computer device 1211 built in accordance withthe present invention is shown which is designed to implement an antennadiversity scheme. A first antenna 1301 is embedded in the cap 1220. Asecond antenna 1302 is shown embedded in the band 1222. As discussed inthe embodiment as shown in FIG. 8, the two antennas 1301 and 1302 sharea common ground contact 1307. The first antenna 1301 is connected to asignal contact 1305. Likewise, the second antenna 1302 is connected to asignal contact 1306. The hole 1249 in the shield 1248 which prevent thesignal contacts 1305 and 1306 from grounding is shown in dashed lines.

The first antenna 1301 is similar to the second antenna 1302 and bothare designed to transmit and receive similar radio frequency signals.When the cap 1220 is engaged in the opening of the housing 1212, thefirst antenna 1301 and the second antenna 1302 will be perpendicularwith respect to each other. The quality of the signal received by thefirst antenna 1301 and the quality of the signal received by the secondantenna 1302 may be greatly different since the antennas are place atright angles with respect to each other. In the present embodiment, theradio card can check the quality of each signal and use the antennawhich is currently receiving the stronger signal. Additionally, it canswitch to the other antenna when the conditions change such that thesignal is no longer acceptable. Utilizing two similar antennas in thismatter, antenna diversification, can be very important in computerterminals of this type since they are often mobile and are oftensubjected to a rapidly changing environment. An antenna diversificationscheme of this type can be used to help eliminate the reception problemsassociated with signal multipath.

Referring now to FIG. 44, another embodiment of the present invention isshown with the first antenna 1311 and the second antenna 1312 attachedto the housing 1212 of the computer terminal 1211. As in the embodimentshown in FIG. 43, the first antenna 1311 is similar to the secondantenna 1312 and both are designed to transmit and receive similar radiofrequency signals and are perpendicular with respect to each other suchthat an antenna diversity scheme can be implemented. The antennas 1311and 1312 are connected to the contacts 1305, 1306 and 1307 through thecap 1220 and though the band 1212.

Referring to FIG. 46, the embodiment of FIG. 44 is shown with the onlydifferences being that the first antenna 1321 and the second antenna1322 are positioned slightly differently and the antennas are designedto transmit and receive different radio frequency signals. Thus, theradio card uses the signal on contact 1305 when it wants to receivesignals via the first antenna 1321 and uses the signal on contact 1306when it wants to receive signal via the second antenna 1322.

In FIGS. 43, 44 and 46, the portion of the connection between thecontacts 1305, 1306 and 1307 and the antennas which pass through theband 1212 are shown schematically as wires. In the best mode of thepresent invention, the transmission of the signal through the band 1212would be accomplished through the use of a micro shield strip 1330 asshown in FIG. 45. The micro shield strip consists of several conductiveribbons running the length of the band 1212 and separated by thenon-conductive material of the band 1212. A wide top ribbon 1333 and awide bottom ribbon 1334 are used to sandwich two smaller ribbons 1336and 1337. The smaller ribbons 1336 and 1337 are used to transmit theantenna signals and are connected to contacts 105 and 106 respectively.The wide bands 1333 and 1334 are common to each other and are used toground each of the antennas and are connected to the ground contact 1307on the cap 1220. The wide ground ribbons 1333 and 1334 shield thesmaller antenna signal ribbons 1336 and 1337 and help to maintain thesignal integrity.

FIG. 47 is a diagram illustrating the use of portable data terminalsaccording to the present invention which utilizes a plurality of radiosto access different subnetworks of an overall communication network.Specifically, subnetworks 1403 and 1405 are illustrated which providefor an overall network environment for MCD 1401. Each subnetwork 1403and 1405 may have a host computer, such as 1407 and 1411, and an accesspoint, such as 1409 and 1413. The access point 1409 provides forcommunication via one type of radio communication while access point1403 provides for another. For example, access point 1409 may provide along-distance digital cellular link while access point 1413 provides forlocal spread spectrum link.

In addition, access points 1409 and 1413 might also exist on a singlenetwork for providing multiple communication paths in case one accesspoint fails or becomes overloaded.

To accommodate multiple radios, the communication module of MCD 1401contains multiple transceivers, and associated protocol substacks andantennas. Specifically, the communication module might include a singleprocessing unit which handles multiple sets of software protocolsubstacks, i.e., one for each of the included transmitters. Similarly,if the protocol substacks and the processing unit functionality of eachradio is too different, additional separate processing units may beincluded. Finally, the ICD (the portable data collection terminal) mightalso be designed to receive multiple communication modules.

In addition, the base module may interrogate the selected (“inserted”)communication module(s) to determine which antennas to interconnect.Alternatively, the communication modules may interrogate the base moduleand request from the available antennas. Where a suitable antenna is notavailable, an external antenna connector is selected. Available antennasmay be installed inside or on the outside of the base unit. Of coursethe antennas might also be selected via the physical communicationmodule connectors as described below.

It should be realized that various other changes and modifications inthe structure of the described embodiment would be possible withoutdeparting from the spirit and scope of the invention as set forth in theclaims.

1-20. (canceled)
 21. A communication device for wireless communicationaccording to a communication protocol comprising a plurality of layers,the device comprising: a base processor operable to perform thefunctionality of a plurality of higher layers of the communicationprotocol; and a communication processor operable to perform thefunctionality of a plurality of lower layers of the communicationprotocol.
 22. The communication device of claim 21 wherein thecommunication processor is operable to perform communication protocolfunctionality associated with power management.
 23. The communicationdevice of claim 22 wherein the power management functionality comprisessupport for sleeping terminals.
 24. The communication device of claim 21wherein the base processor is operable to perform communication protocolfunctionality associated with power management.
 25. The communicationdevice of claim 24 wherein the power management functionality comprisessupport for sleeping terminals.
 26. The communication device of claim 21wherein the communication processor is operable to perform communicationprotocol functionality associated with support for roaming.
 27. Thecommunication device of claim 21 wherein the communication processor isoperable to perform communication protocol functionality associated withsupport for reliable transmission.
 28. The communication device of claim21 wherein the communication processor is operable to perform thefunctionality of a data link layer of the communication protocol. 29.The communication device of claim 21 wherein the communication processoris operable to perform the functionality of a physical layer of thecommunication protocol.
 30. The communication device of claim 21 whereinthe base processor is operable to perform the functionality of asessions layer of the communication protocol.
 31. The communicationdevice of claim 21 wherein the base processor is operable to perform thefunctionality of a transport layer of the communication protocol. 32.The communication device of claim 21 wherein the base processor isoperable to perform the functionality of a network layer of thecommunication protocol.
 33. The communication device of claim 21 whereinthe base processor is operable to perform the functionality of a firstportion of a network layer of the communication protocol and thecommunication processor is operable to perform the functionality of asecond portion of a network layer of the communication protocol.